From patchwork Thu May 27 16:12:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 12284739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9238AC47089 for ; Thu, 27 May 2021 16:14:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 76440613C3 for ; Thu, 27 May 2021 16:14:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237292AbhE0QQA (ORCPT ); Thu, 27 May 2021 12:16:00 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:18740 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S237217AbhE0QPB (ORCPT ); Thu, 27 May 2021 12:15:01 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14RGD6Yx000886; Thu, 27 May 2021 18:13:06 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=gKPsCJ6VkrFXQVm8iT6fA6fi1Wgo7CYCS24MGBMWUS4=; b=63TfMgPKvd/esIagiCiLuyoEcbEwnptxWEdAa7CeezPX2+BRQ+gzBWoFAdDEyUG7d34h njIMIqSM8VrtyrglN/835s53hX2T+VuzkWfU4mPHKPkNziuGiMCsGBID7+Nhy3XhyRPl irYgo5xG+tY29Rg2M5oEWe+t8Vn3q3qDaVxDVUCdGV6R8rfeGondLfP28OP6PGqdZTiM I7STtD96FaIpv3pbQvMtqdtCHh8Xp5EgrjdlkiirvORD7NEJzqXjT0ic6qv5ffwvyGWu zFR6aptcQTBpTmZsDkB+yoqkp13/Sy0ezinu97IOIwq3U5ZlqXfDOt59rmlI/Y6ttdci ow== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 38t7k3av09-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 May 2021 18:13:06 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8449C100038; Thu, 27 May 2021 18:13:04 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7620D236565; Thu, 27 May 2021 18:13:04 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 18:13:04 +0200 From: To: Mark Brown , Miquel Raynal , Vignesh Raghavendra , Boris Brezillon , , Alexandre Torgue , , , , CC: , Subject: [PATCH v3 2/3] mtd: spinand: add spinand_read_cfg() helper Date: Thu, 27 May 2021 18:12:51 +0200 Message-ID: <20210527161252.16620-3-patrice.chotard@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527161252.16620-1-patrice.chotard@foss.st.com> References: <20210527161252.16620-1-patrice.chotard@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-05-27_09:2021-05-27,2021-05-27 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Patrice Chotard Put REG_CFG reading code in spinand_read_cfg(). This function will be needed by the future SPI-NAND resume ops. Signed-off-by: Patrice Chotard --- drivers/mtd/nand/spi/core.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 095742e5bc2b..1f699ad84f1b 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -138,20 +138,12 @@ int spinand_select_target(struct spinand_device *spinand, unsigned int target) return 0; } -static int spinand_init_cfg_cache(struct spinand_device *spinand) +static int spinand_read_cfg(struct spinand_device *spinand) { struct nand_device *nand = spinand_to_nand(spinand); - struct device *dev = &spinand->spimem->spi->dev; unsigned int target; int ret; - spinand->cfg_cache = devm_kcalloc(dev, - nand->memorg.ntargets, - sizeof(*spinand->cfg_cache), - GFP_KERNEL); - if (!spinand->cfg_cache) - return -ENOMEM; - for (target = 0; target < nand->memorg.ntargets; target++) { ret = spinand_select_target(spinand, target); if (ret) @@ -170,6 +162,21 @@ static int spinand_init_cfg_cache(struct spinand_device *spinand) return 0; } +static int spinand_init_cfg_cache(struct spinand_device *spinand) +{ + struct nand_device *nand = spinand_to_nand(spinand); + struct device *dev = &spinand->spimem->spi->dev; + + spinand->cfg_cache = devm_kcalloc(dev, + nand->memorg.ntargets, + sizeof(*spinand->cfg_cache), + GFP_KERNEL); + if (!spinand->cfg_cache) + return -ENOMEM; + + return spinand_read_cfg(spinand); +} + static int spinand_init_quad_enable(struct spinand_device *spinand) { bool enable = false;