| Message ID | 20210608022644.21074-5-jon.lin@rock-chips.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Rockchip SFC(serial flash controller) support | expand |
Hi Jon, For rk3036 we might need another fix added to this serie as well. clk: rockchip: rk3036: fix up the sclk_sfc parent error https://github.com/rockchip-linux/kernel/commit/100718ef0d44872db1672b6a88030374c0d1613b === Add more people for clk driver changes: M: Michael Turquette <mturquette@baylibre.com> M: Stephen Boyd <sboyd@kernel.org> L: linux-clk@vger.kernel.org === Johan On 6/8/21 4:26 AM, Jon Lin wrote: > From: Chris Morgan <macromorgan@hotmail.com> From: Randy Li <randy.li@rock-chips.com> > > Add support for the bus clock for the serial flash controller on the > rk3036. Taken from the Rockchip BSP kernel but not tested on real > hardware (as I lack a 3036 based SoC to test). > Signed-off-by: Randy Li <randy.li@rock-chips.com> Maybe give credit to the original author? clk: rockchip: rk3036: export the sfc clocks https://github.com/rockchip-linux/kernel/commit/600925e8ef6edbdda0a4ac6b3c55b0199be1e03e > Signed-off-by: Chris Morgan <macromorgan@hotmail.com> > Signed-off-by: Jon Lin <jon.lin@rock-chips.com> > --- > > Changes in v6: None > Changes in v5: None > Changes in v4: None > Changes in v3: None > Changes in v2: None > Changes in v1: None > > drivers/clk/rockchip/clk-rk3036.c | 2 +- > include/dt-bindings/clock/rk3036-cru.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c > index 91d56ad45817..ebb628733f6d 100644 > --- a/drivers/clk/rockchip/clk-rk3036.c > +++ b/drivers/clk/rockchip/clk-rk3036.c > @@ -403,7 +403,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { > GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), > GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), > GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), > - GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), > + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), Maybe CLK_IGNORE_UNUSED should be changed to 0 ? > GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), > > /* pclk_peri gates */ > diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h > index 35a5a01f9697..a96a9870ad59 100644 > --- a/include/dt-bindings/clock/rk3036-cru.h > +++ b/include/dt-bindings/clock/rk3036-cru.h > @@ -81,6 +81,7 @@ > #define HCLK_OTG0 449 > #define HCLK_OTG1 450 > #define HCLK_NANDC 453 > +#define HCLK_SFC 454 > #define HCLK_SDMMC 456 > #define HCLK_SDIO 457 > #define HCLK_EMMC 459 >
On 6/9/21 12:31 AM, Johan Jonker wrote: > Hi Jon, > > For rk3036 we might need another fix added to this serie as well. > > clk: rockchip: rk3036: fix up the sclk_sfc parent error > https://github.com/rockchip-linux/kernel/commit/100718ef0d44872db1672b6a88030374c0d1613b > > === > Add more people for clk driver changes: > > M: Michael Turquette <mturquette@baylibre.com> > M: Stephen Boyd <sboyd@kernel.org> > L: linux-clk@vger.kernel.org > > === > > Johan > > On 6/8/21 4:26 AM, Jon Lin wrote: > >> From: Chris Morgan <macromorgan@hotmail.com> > From: Randy Li <randy.li@rock-chips.com> > >> Add support for the bus clock for the serial flash controller on the >> rk3036. Taken from the Rockchip BSP kernel but not tested on real >> hardware (as I lack a 3036 based SoC to test). >> > Signed-off-by: Randy Li <randy.li@rock-chips.com> > > Maybe give credit to the original author? > clk: rockchip: rk3036: export the sfc clocks > https://github.com/rockchip-linux/kernel/commit/600925e8ef6edbdda0a4ac6b3c55b0199be1e03e something wrong when I add randy.li@rock-chips.com email, I will make a confirmation with it with him. >> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> >> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> >> --- >> >> Changes in v6: None >> Changes in v5: None >> Changes in v4: None >> Changes in v3: None >> Changes in v2: None >> Changes in v1: None >> >> drivers/clk/rockchip/clk-rk3036.c | 2 +- >> include/dt-bindings/clock/rk3036-cru.h | 1 + >> 2 files changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c >> index 91d56ad45817..ebb628733f6d 100644 >> --- a/drivers/clk/rockchip/clk-rk3036.c >> +++ b/drivers/clk/rockchip/clk-rk3036.c >> @@ -403,7 +403,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { >> GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), >> GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), >> GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), >> - GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), >> + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), > Maybe CLK_IGNORE_UNUSED should be changed to 0 ? > >> GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), >> >> /* pclk_peri gates */ >> diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h >> index 35a5a01f9697..a96a9870ad59 100644 >> --- a/include/dt-bindings/clock/rk3036-cru.h >> +++ b/include/dt-bindings/clock/rk3036-cru.h >> @@ -81,6 +81,7 @@ >> #define HCLK_OTG0 449 >> #define HCLK_OTG1 450 >> #define HCLK_NANDC 453 >> +#define HCLK_SFC 454 >> #define HCLK_SDMMC 456 >> #define HCLK_SDIO 457 >> #define HCLK_EMMC 459 >> > >
On 6/9/21 12:31 AM, Johan Jonker wrote: > Hi Jon, > > For rk3036 we might need another fix added to this serie as well. > > clk: rockchip: rk3036: fix up the sclk_sfc parent error > https://github.com/rockchip-linux/kernel/commit/100718ef0d44872db1672b6a88030374c0d1613b > > === > Add more people for clk driver changes: > > M: Michael Turquette <mturquette@baylibre.com> > M: Stephen Boyd <sboyd@kernel.org> > L: linux-clk@vger.kernel.org > > === > > Johan > > On 6/8/21 4:26 AM, Jon Lin wrote: > >> From: Chris Morgan <macromorgan@hotmail.com> > From: Randy Li <randy.li@rock-chips.com> > >> Add support for the bus clock for the serial flash controller on the >> rk3036. Taken from the Rockchip BSP kernel but not tested on real >> hardware (as I lack a 3036 based SoC to test). >> > Signed-off-by: Randy Li <randy.li@rock-chips.com> > > Maybe give credit to the original author? > clk: rockchip: rk3036: export the sfc clocks > https://github.com/rockchip-linux/kernel/commit/600925e8ef6edbdda0a4ac6b3c55b0199be1e03e Randy Li has resigned from RK >> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> >> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> >> --- >> >> Changes in v6: None >> Changes in v5: None >> Changes in v4: None >> Changes in v3: None >> Changes in v2: None >> Changes in v1: None >> >> drivers/clk/rockchip/clk-rk3036.c | 2 +- >> include/dt-bindings/clock/rk3036-cru.h | 1 + >> 2 files changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c >> index 91d56ad45817..ebb628733f6d 100644 >> --- a/drivers/clk/rockchip/clk-rk3036.c >> +++ b/drivers/clk/rockchip/clk-rk3036.c >> @@ -403,7 +403,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { >> GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), >> GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), >> GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), >> - GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), >> + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), > Maybe CLK_IGNORE_UNUSED should be changed to 0 ? > >> GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), >> >> /* pclk_peri gates */ >> diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h >> index 35a5a01f9697..a96a9870ad59 100644 >> --- a/include/dt-bindings/clock/rk3036-cru.h >> +++ b/include/dt-bindings/clock/rk3036-cru.h >> @@ -81,6 +81,7 @@ >> #define HCLK_OTG0 449 >> #define HCLK_OTG1 450 >> #define HCLK_NANDC 453 >> +#define HCLK_SFC 454 >> #define HCLK_SDMMC 456 >> #define HCLK_SDIO 457 >> #define HCLK_EMMC 459 >> > >
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 91d56ad45817..ebb628733f6d 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -403,7 +403,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), - GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), /* pclk_peri gates */ diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 35a5a01f9697..a96a9870ad59 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -81,6 +81,7 @@ #define HCLK_OTG0 449 #define HCLK_OTG1 450 #define HCLK_NANDC 453 +#define HCLK_SFC 454 #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459