From patchwork Mon Jul 19 07:48:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12384935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78A98C12002 for ; Mon, 19 Jul 2021 07:48:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4DB5461019 for ; Mon, 19 Jul 2021 07:48:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234943AbhGSHvd (ORCPT ); Mon, 19 Jul 2021 03:51:33 -0400 Received: from mga05.intel.com ([192.55.52.43]:14956 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234892AbhGSHva (ORCPT ); Mon, 19 Jul 2021 03:51:30 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10049"; a="296571128" X-IronPort-AV: E=Sophos;i="5.84,251,1620716400"; d="scan'208";a="296571128" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2021 00:48:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,251,1620716400"; d="scan'208";a="495724107" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 19 Jul 2021 00:48:19 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id ACDFC23A; Mon, 19 Jul 2021 10:48:46 +0300 (EEST) From: Andy Shevchenko To: Mark Brown , Andy Shevchenko , linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Daniel Mack , Haojian Zhuang , Robert Jarzmik Subject: [PATCH v1 2/3] spi: pxa2xx: Reset DMA bits in CR1 in reset_sccr1() Date: Mon, 19 Jul 2021 10:48:41 +0300 Message-Id: <20210719074842.36060-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210719074842.36060-1-andriy.shevchenko@linux.intel.com> References: <20210719074842.36060-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org In order to allow reset_sccr1() to be reused in DMA paths, reset DMA bits in CR1 in this function. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 7c4c8179a329..833eb52ed305 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -595,7 +595,7 @@ static int u32_reader(struct driver_data *drv_data) static void reset_sccr1(struct driver_data *drv_data) { struct chip_data *chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); - u32 mask = drv_data->int_cr1; + u32 mask = drv_data->int_cr1 | drv_data->dma_cr1; switch (drv_data->ssp_type) { case QUARK_X1000_SSP: