| Message ID | 20211025015156.33133-12-brad@pensando.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support Pensando Elba SoC | expand |
Hi, On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > Add Pensando common and Elba SoC specific device nodes > > Signed-off-by: Brad Larson <brad@pensando.io> [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>; > + }; The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you have GICv3, where this is not valid, so this should go. Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which doesn't mak sense for the 16 CPUs you have. > + gic: interrupt-controller@800000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gic_its: msi-controller@820000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x0 0x820000 0x0 0x10000>; > + socionext,synquacer-pre-its = > + <0xc00000 0x1000000>; > + }; > + }; Is there any shared lineage with Synquacer? The commit message didn't describe this quirk. Thanks, Mark.
On 2021-10-25 10:17, Mark Rutland wrote: > Hi, > > On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: >> Add Pensando common and Elba SoC specific device nodes >> >> Signed-off-by: Brad Larson <brad@pensando.io> > > [...] > >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | >> + IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | >> + IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | >> + IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | >> + IRQ_TYPE_LEVEL_LOW)>; >> + }; > > The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you > have GICv3, where this is not valid, so this should go. > > Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which > doesn't mak sense for the 16 CPUs you have. > >> + gic: interrupt-controller@800000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + interrupt-controller; >> + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ >> + <0x0 0xa00000 0x0 0x200000>; /* GICR */ This is missing the GICv2 compat regions that the CPUs implement. >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + >> + gic_its: msi-controller@820000 { >> + compatible = "arm,gic-v3-its"; >> + msi-controller; >> + #msi-cells = <1>; >> + reg = <0x0 0x820000 0x0 0x10000>; >> + socionext,synquacer-pre-its = >> + <0xc00000 0x1000000>; >> + }; >> + }; > > Is there any shared lineage with Synquacer? The commit message didn't > describe this quirk. Funny, it looks like there is a sudden outburst of stupid copy/paste among HW designers. TI did the exact same thing recently. This totally negates all the advantages of having an ITS and makes sure that you have all the overhead. Facepalm... M.
On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > Add Pensando common and Elba SoC specific device nodes > > Signed-off-by: Brad Larson <brad@pensando.io> > --- > Changelog: > - Node names changed to DT generic names > - Changed from using 'spi@' which is reserved > - The elba-flash-parts.dtsi is kept separate as > it is included in multiple dts files. > - SPDX license tags at the top of each file > - The compatible = "pensando,elba" and 'model' are > now together in the board file. > - UIO nodes removed > - Ordered nodes by increasing unit address > - Removed an unreferenced container node. > - Dropped deprecated 'device_type' for uart0 node. > > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/pensando/Makefile | 6 + > arch/arm64/boot/dts/pensando/elba-16core.dtsi | 192 ++++++++++++++++++ > .../boot/dts/pensando/elba-asic-common.dtsi | 96 +++++++++ > arch/arm64/boot/dts/pensando/elba-asic.dts | 23 +++ > .../boot/dts/pensando/elba-flash-parts.dtsi | 103 ++++++++++ > arch/arm64/boot/dts/pensando/elba.dtsi | 181 +++++++++++++++++ > 7 files changed, 602 insertions(+) > create mode 100644 arch/arm64/boot/dts/pensando/Makefile > create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi > create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi > create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts > create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi > create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi > > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 639e01a4d855..34f99a99c488 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -20,6 +20,7 @@ subdir-y += marvell > subdir-y += mediatek > subdir-y += microchip > subdir-y += nvidia > +subdir-y += pensando > subdir-y += qcom > subdir-y += realtek > subdir-y += renesas > diff --git a/arch/arm64/boot/dts/pensando/Makefile b/arch/arm64/boot/dts/pensando/Makefile > new file mode 100644 > index 000000000000..61031ec11838 > --- /dev/null > +++ b/arch/arm64/boot/dts/pensando/Makefile > @@ -0,0 +1,6 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb > + > +always-y := $(dtb-y) > +subdir-y := $(dts-dirs) > +clean-files := *.dtb None of these lines should be needed. > diff --git a/arch/arm64/boot/dts/pensando/elba-16core.dtsi b/arch/arm64/boot/dts/pensando/elba-16core.dtsi > new file mode 100644 > index 000000000000..acf5941afbc1 > --- /dev/null > +++ b/arch/arm64/boot/dts/pensando/elba-16core.dtsi > @@ -0,0 +1,192 @@ > +// SPDX-License-Identifier: GPL-2.0 Do you care about using with non-GPL OS? Dual license is preferred. > + > +/ { > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { cpu = <&cpu0>; }; > + core1 { cpu = <&cpu1>; }; > + core2 { cpu = <&cpu2>; }; > + core3 { cpu = <&cpu3>; }; > + }; > + > + cluster1 { > + core0 { cpu = <&cpu4>; }; > + core1 { cpu = <&cpu5>; }; > + core2 { cpu = <&cpu6>; }; > + core3 { cpu = <&cpu7>; }; > + }; > + > + cluster2 { > + core0 { cpu = <&cpu8>; }; > + core1 { cpu = <&cpu9>; }; > + core2 { cpu = <&cpu10>; }; > + core3 { cpu = <&cpu11>; }; > + }; > + > + cluster3 { > + core0 { cpu = <&cpu12>; }; > + core1 { cpu = <&cpu13>; }; > + core2 { cpu = <&cpu14>; }; > + core3 { cpu = <&cpu15>; }; > + }; > + }; > + > + /* CLUSTER 0 */ > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x0>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x1>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x2>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x3>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + l2_0: l2-cache0 { > + compatible = "cache"; > + }; > + > + /* CLUSTER 1 */ > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x100>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x101>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x102>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x103>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + l2_1: l2-cache1 { > + compatible = "cache"; > + }; > + > + /* CLUSTER 2 */ > + cpu8: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x200>; > + next-level-cache = <&l2_2>; > + enable-method = "psci"; > + }; > + > + cpu9: cpu@201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x201>; > + next-level-cache = <&l2_2>; > + enable-method = "psci"; > + }; > + > + cpu10: cpu@202 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x202>; > + next-level-cache = <&l2_2>; > + enable-method = "psci"; > + }; > + > + cpu11: cpu@203 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x203>; > + next-level-cache = <&l2_2>; > + enable-method = "psci"; > + }; > + > + l2_2: l2-cache2 { > + compatible = "cache"; > + }; > + > + /* CLUSTER 3 */ > + cpu12: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x300>; > + next-level-cache = <&l2_3>; > + enable-method = "psci"; > + }; > + > + cpu13: cpu@301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x301>; > + next-level-cache = <&l2_3>; > + enable-method = "psci"; > + }; > + > + cpu14: cpu@302 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x302>; > + next-level-cache = <&l2_3>; > + enable-method = "psci"; > + }; > + > + cpu15: cpu@303 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x303>; > + next-level-cache = <&l2_3>; > + enable-method = "psci"; > + }; > + > + l2_3: l2-cache3 { > + compatible = "cache"; > + }; > + > + psci { This goes at the root level. > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + }; > +}; > diff --git a/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi > new file mode 100644 > index 000000000000..ba584c0fe0d5 > --- /dev/null > +++ b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi > @@ -0,0 +1,96 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Copyright (c) 2019-2021, Pensando Systems Inc. */ > + > +&ahb_clk { > + clock-frequency = <400000000>; > +}; > + > +&emmc_clk { > + clock-frequency = <200000000>; > +}; > + > +&flash_clk { > + clock-frequency = <400000000>; > +}; > + > +&ref_clk { > + clock-frequency = <156250000>; > +}; > + > +&qspi { > + status = "okay"; > + flash0: flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <40000000>; > + spi-rx-bus-width = <2>; > + m25p,fast-read; > + cdns,read-delay = <0>; > + cdns,tshsl-ns = <0>; > + cdns,tsd2d-ns = <0>; > + cdns,tchsh-ns = <0>; > + cdns,tslch-ns = <0>; > + }; > +}; > + > +&gpio0 { > + status = "okay"; > +}; > + > +&emmc { > + bus-width = <8>; > + status = "okay"; > +}; > + > +&wdt0 { > + status = "okay"; > +}; > + > +&i2c0 { > + clock-frequency = <100000>; > + status = "okay"; > + rtc@51 { > + compatible = "nxp,pcf85263"; > + reg = <0x51>; > + }; > +}; > + > +&spi0 { > + num-cs = <4>; > + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, > + <&porta 7 GPIO_ACTIVE_LOW>; > + status = "okay"; > + spi0_cs0@0 { Node names should reflect the class of device and use standard name defined in the DT spec. This probably doesn't have one. 'lora' perhaps? > + compatible = "semtech,sx1301"; /* Enable spidev */ What's spidev? > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <12000000>; > + reg = <0>; > + }; > + > + spi0_cs1@1 { > + compatible = "semtech,sx1301"; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <12000000>; > + reg = <1>; > + }; > + > + spi0_cs2@2 { > + compatible = "semtech,sx1301"; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <12000000>; > + reg = <2>; > + interrupt-parent = <&porta>; > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + spi0_cs3@3 { > + compatible = "semtech,sx1301"; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <12000000>; > + reg = <3>; > + }; > +}; > diff --git a/arch/arm64/boot/dts/pensando/elba-asic.dts b/arch/arm64/boot/dts/pensando/elba-asic.dts > new file mode 100644 > index 000000000000..131931dc643f > --- /dev/null > +++ b/arch/arm64/boot/dts/pensando/elba-asic.dts > @@ -0,0 +1,23 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +/dts-v1/; > + > +/ { > + model = "Elba ASIC Board"; > + compatible = "pensando,elba"; Normally we have a compatible for the board plus the soc compatible. > + > + aliases { > + serial0 = &uart0; > + spi0 = &spi0; > + spi1 = &qspi; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +#include "elba.dtsi" > +#include "elba-16core.dtsi" > +#include "elba-asic-common.dtsi" > +#include "elba-flash-parts.dtsi" > diff --git a/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi > new file mode 100644 > index 000000000000..e69734c2c267 > --- /dev/null > +++ b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi > @@ -0,0 +1,103 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +&flash0 { > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + partition@0 { > + label = "flash"; > + reg = <0x10000 0xfff0000>; > + }; > + > + partition@f0000 { > + label = "golduenv"; > + reg = <0xf0000 0x10000>; > + }; > + > + partition@100000 { > + label = "boot0"; > + reg = <0x100000 0x80000>; > + }; > + > + partition@180000 { > + label = "golduboot"; > + reg = <0x180000 0x200000>; > + }; > + > + partition@380000 { > + label = "brdcfg0"; > + reg = <0x380000 0x10000>; > + }; > + > + partition@390000 { > + label = "brdcfg1"; > + reg = <0x390000 0x10000>; > + }; > + > + partition@400000 { > + label = "goldfw"; > + reg = <0x400000 0x3c00000>; > + }; > + > + partition@4010000 { > + label = "fwmap"; > + reg = <0x4010000 0x20000>; > + }; > + > + partition@4030000 { > + label = "fwsel"; > + reg = <0x4030000 0x20000>; > + }; > + > + partition@4090000 { > + label = "bootlog"; > + reg = <0x4090000 0x20000>; > + }; > + > + partition@40b0000 { > + label = "panicbuf"; > + reg = <0x40b0000 0x20000>; > + }; > + > + partition@40d0000 { > + label = "uservars"; > + reg = <0x40d0000 0x20000>; > + }; > + > + partition@4200000 { > + label = "uboota"; > + reg = <0x4200000 0x400000>; > + }; > + > + partition@4600000 { > + label = "ubootb"; > + reg = <0x4600000 0x400000>; > + }; > + > + partition@4a00000 { > + label = "mainfwa"; > + reg = <0x4a00000 0x1000000>; > + }; > + > + partition@5a00000 { > + label = "mainfwb"; > + reg = <0x5a00000 0x1000000>; > + }; > + > + partition@6a00000 { > + label = "diaguboot"; > + reg = <0x6a00000 0x400000>; > + }; > + > + partition@8000000 { > + label = "diagfw"; > + reg = <0x8000000 0x7fe0000>; > + }; > + > + partition@ffe0000 { > + label = "ubootenv"; > + reg = <0xffe0000 0x10000>; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/pensando/elba.dtsi b/arch/arm64/boot/dts/pensando/elba.dtsi > new file mode 100644 > index 000000000000..b28f69e0bd91 > --- /dev/null > +++ b/arch/arm64/boot/dts/pensando/elba.dtsi > @@ -0,0 +1,181 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Copyright (c) 2019-2021, Pensando Systems Inc. */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include "dt-bindings/interrupt-controller/arm-gic.h" > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + dma-coherent; > + > + ahb_clk: oscillator0 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + emmc_clk: oscillator2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + flash_clk: oscillator3 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + ref_clk: oscillator4 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + pmu { > + compatible = "arm,cortex-a72-pmu"; > + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + soc: soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + i2c0: i2c@400 { > + compatible = "snps,designware-i2c"; > + reg = <0x0 0x400 0x0 0x100>; > + clocks = <&ahb_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + i2c-sda-hold-time-ns = <480>; > + snps,sda-timeout-ms = <750>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + wdt0: watchdog@1400 { > + compatible = "snps,dw-wdt"; > + reg = <0x0 0x1400 0x0 0x100>; > + clocks = <&ahb_clk>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + qspi: spi@2400 { > + compatible = "pensando,elba-qspi", "cdns,qspi-nor"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2400 0x0 0x400>, > + <0x0 0x7fff0000 0x0 0x1000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&flash_clk>; > + cdns,fifo-depth = <1024>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x7fff0000>; > + status = "disabled"; > + }; > + > + spi0: spi@2800 { > + compatible = "pensando,elba-spi"; > + reg = <0x0 0x2800 0x0 0x100>; > + pensando,spics = <&mssoc 0x2468>; > + clocks = <&ahb_clk>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + num-cs = <2>; > + status = "disabled"; > + }; > + > + gpio0: gpio@4000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dw-apb-gpio"; > + reg = <0x0 0x4000 0x0 0x78>; > + status = "disabled"; > + > + porta: gpio-port@0 { > + compatible = "snps,dw-apb-gpio-port"; > + reg = <0>; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <8>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + interrupt-parent = <&gic>; > + #interrupt-cells = <2>; > + }; > + > + portb: gpio-port@1 { > + compatible = "snps,dw-apb-gpio-port"; > + reg = <1>; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <8>; > + }; > + }; > + > + uart0: serial@4800 { > + compatible = "ns16550a"; > + reg = <0x0 0x4800 0x0 0x100>; > + clocks = <&ref_clk>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + }; > + > + gic: interrupt-controller@800000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gic_its: msi-controller@820000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x0 0x820000 0x0 0x10000>; > + socionext,synquacer-pre-its = > + <0xc00000 0x1000000>; > + }; > + }; > + > + emmc: mmc@30440000 { > + compatible = "pensando,elba-emmc", "cdns,sd4hc"; > + clocks = <&emmc_clk>; > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x30440000 0x0 0x10000>, > + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ > + cdns,phy-input-delay-sd-highspeed = <0x4>; > + cdns,phy-input-delay-legacy = <0x4>; > + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; > + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; > + mmc-ddr-1_8v; > + status = "disabled"; > + }; > + > + mssoc: mssoc@307c0000 { > + compatible = "syscon", "simple-mfd"; > + reg = <0x0 0x307c0000 0x0 0x3000>; > + }; > + }; > +}; > -- > 2.17.1 > >
Hi Mark, On Mon, Oct 25, 2021 at 2:17 AM Mark Rutland <mark.rutland@arm.com> wrote: > > Hi, > > On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > > Add Pensando common and Elba SoC specific device nodes > > > > Signed-off-by: Brad Larson <brad@pensando.io> > > [...] > > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | > > + IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | > > + IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | > > + IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | > > + IRQ_TYPE_LEVEL_LOW)>; > > + }; > > The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you > have GICv3, where this is not valid, so this should go. > > Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which > doesn't mak sense for the 16 CPUs you have. > Thanks for pointing this out. Elba SoC is a GICv3 implementation and looking at other device tree files we should be using this: timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(16) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(16) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(16) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(16) | IRQ_TYPE_LEVEL_LOW)>; }; > > + gic: interrupt-controller@800000 { > > + compatible = "arm,gic-v3"; > > + #interrupt-cells = <3>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + interrupt-controller; > > + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > > + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > + > > + gic_its: msi-controller@820000 { > > + compatible = "arm,gic-v3-its"; > > + msi-controller; > > + #msi-cells = <1>; > > + reg = <0x0 0x820000 0x0 0x10000>; > > + socionext,synquacer-pre-its = > > + <0xc00000 0x1000000>; > > + }; > > + }; > > Is there any shared lineage with Synquacer? The commit message didn't > describe this quirk. There is no shared lineage with Synqacer. We are solving the same issue with the same mechanism. I'll add a comment to this DTS node. Thanks, Brad
Hi Marc, On Mon, Oct 25, 2021 at 4:15 AM Marc Zyngier <maz@kernel.org> wrote: > > On 2021-10-25 10:17, Mark Rutland wrote: > > Hi, > > > > On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > >> Add Pensando common and Elba SoC specific device nodes > >> > >> Signed-off-by: Brad Larson <brad@pensando.io> > > > > [...] > >> + gic: interrupt-controller@800000 { > >> + compatible = "arm,gic-v3"; > >> + #interrupt-cells = <3>; > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + ranges; > >> + interrupt-controller; > >> + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > >> + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > > This is missing the GICv2 compat regions that the CPUs implement. Is this what is described as optional in the GIC architecture specification where a GICv3 system can run restricted GICv2 code? Can you point me in the right direction in the spec and example dts node if needed. > >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > >> + > >> + gic_its: msi-controller@820000 { > >> + compatible = "arm,gic-v3-its"; > >> + msi-controller; > >> + #msi-cells = <1>; > >> + reg = <0x0 0x820000 0x0 0x10000>; > >> + socionext,synquacer-pre-its = > >> + <0xc00000 0x1000000>; > >> + }; > >> + }; > > > > Is there any shared lineage with Synquacer? The commit message didn't > > describe this quirk. > > Funny, it looks like there is a sudden outburst of stupid copy/paste > among HW designers. TI did the exact same thing recently. > > This totally negates all the advantages of having an ITS and makes > sure that you have all the overhead. Facepalm... Some background may help explain. To generate an LPI a peripheral must write to the GITS_TRANSLATER (a specific address). For the ITS to know which translations apply to the generated interrupts, it must know which peripheral performed the write. The ID of the peripheral is known as its DeviceID, which is often carried along with the write as an AXI sideband signal. The Elba SoC doesn't carry the DeviceID, so we have to conjure one up between the peripheral and the ITS. Instead of telling a peripheral to target the GITS_TRANSLATER directly, we instead direct it to a specific offset within a pre-ITS address range (our own IP block). For writes that land in that memory range, we derive the DeviceID from (offset >> 2). The pre-ITS block then sends (DeviceID, data) to the GITS_TRANSLATER. The hardware designer came up with the Pre-ITS mechanism in Feb 2018. When we looked at the upstream kernel later (we developed on 4.14) we found that not only did it support something similar, it supported the exact scheme we are using. Thanks, Brad
Brad, On Fri, 05 Nov 2021 00:02:04 +0000, Brad Larson <brad@pensando.io> wrote: > > Hi Marc, > > On Mon, Oct 25, 2021 at 4:15 AM Marc Zyngier <maz@kernel.org> wrote: > > > > On 2021-10-25 10:17, Mark Rutland wrote: > > > Hi, > > > > > > On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > > >> Add Pensando common and Elba SoC specific device nodes > > >> > > >> Signed-off-by: Brad Larson <brad@pensando.io> > > > > > > [...] > > >> + gic: interrupt-controller@800000 { > > >> + compatible = "arm,gic-v3"; > > >> + #interrupt-cells = <3>; > > >> + #address-cells = <2>; > > >> + #size-cells = <2>; > > >> + ranges; > > >> + interrupt-controller; > > >> + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > > >> + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > > > > This is missing the GICv2 compat regions that the CPUs implement. > > Is this what is described as optional in the GIC architecture specification > where a GICv3 system can run restricted GICv2 code? Yup, that. It is actually implemented by the CPU. > Can you point me in the right direction in the spec and example dts > node if needed. The Cortex-A72 TRM has everything you need [1]. And since you used the Synquacer as the model for this, you will see that it has the missing regions. Alternatively, rk3399.dtsi is a good example. > > >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > >> + > > >> + gic_its: msi-controller@820000 { > > >> + compatible = "arm,gic-v3-its"; > > >> + msi-controller; > > >> + #msi-cells = <1>; > > >> + reg = <0x0 0x820000 0x0 0x10000>; > > >> + socionext,synquacer-pre-its = > > >> + <0xc00000 0x1000000>; > > >> + }; > > >> + }; > > > > > > Is there any shared lineage with Synquacer? The commit message didn't > > > describe this quirk. > > > > Funny, it looks like there is a sudden outburst of stupid copy/paste > > among HW designers. TI did the exact same thing recently. > > > > This totally negates all the advantages of having an ITS and makes > > sure that you have all the overhead. Facepalm... > > Some background may help explain. To generate an LPI a peripheral must > write to the GITS_TRANSLATER (a specific address). For the ITS to know > which translations apply to the generated interrupts, it must know which > peripheral performed the write. The ID of the peripheral is known as its > DeviceID, which is often carried along with the write as an AXI sideband > signal. Yes, I happen to be vaguely familiar with the GIC architecture. > The Elba SoC doesn't carry the DeviceID, so we have to conjure one up > between the peripheral and the ITS. Instead of telling a peripheral to target > the GITS_TRANSLATER directly, we instead direct it to a specific offset > within a pre-ITS address range (our own IP block). For writes that land in > that memory range, we derive the DeviceID from (offset >> 2). The pre-ITS > block then sends (DeviceID, data) to the GITS_TRANSLATER. > > The hardware designer came up with the Pre-ITS mechanism in Feb 2018. > When we looked at the upstream kernel later (we developed on 4.14) > we found that not only did it support something similar, it supported the > exact scheme we are using. And this scheme is totally wrong. It breaks interrupt isolation. Instead of having a single doorbell and getting the ITS to segregate between devices itself, you end-up with multiple ones, allowing a rogue device to impersonate another one by targeting another doorbell. You can't even use an SMMU to preserve some isolation, because all the doorbells are in the *same page*. Unmitigated disaster. At this stage, why did you bother having an ITS at all? You get none of the security features. Only the excess area, memory allocation, additional latency and complexity. All you get is a larger INTID space. This only shows that the hardware designer didn't understand the ITS at all. Which seems a common pattern, unfortunately. M. [1] https://developer.arm.com/documentation/100095/0003/Generic-Interrupt-Controller-CPU-Interface/GIC-functional-description/GIC-memory-map?lang=en#way1382452674438__CHDEBJAJ
On Thu, Nov 04, 2021 at 03:53:13PM -0700, Brad Larson wrote: > On Mon, Oct 25, 2021 at 2:17 AM Mark Rutland <mark.rutland@arm.com> wrote: > > On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > > > + timer { > > > + compatible = "arm,armv8-timer"; > > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | > > > + IRQ_TYPE_LEVEL_LOW)>, > > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | > > > + IRQ_TYPE_LEVEL_LOW)>, > > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | > > > + IRQ_TYPE_LEVEL_LOW)>, > > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | > > > + IRQ_TYPE_LEVEL_LOW)>; > > > + }; > > > > The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you > > have GICv3, where this is not valid, so this should go. > > > > Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which > > doesn't mak sense for the 16 CPUs you have. > > > > Thanks for pointing this out. Elba SoC is a GICv3 implementation and looking > at other device tree files we should be using this: > > timer { > compatible = "arm,armv8-timer"; > interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(16) | > IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(16) | > IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(16) | > IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(16) | > IRQ_TYPE_LEVEL_LOW)>; > }; No; as above, you should *not* use GIC_CPU_MASK_SIMPLE() at all for GICv3. i.e. > timer { > compatible = "arm,armv8-timer"; > interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; > }; Please see the GICv3 binding documentation: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml ... and note that it does not have the cpumask field as use by the binding for prior generations of GIC: Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml If you've seen other dts files using GIC_CPU_MASK_SIMPLE() with GICv3, those are incorrect, and need to be fixed. Thanks, Mark.
Hi Mark, On Mon, Nov 8, 2021 at 2:26 AM Mark Rutland <mark.rutland@arm.com> wrote: > > No; as above, you should *not* use GIC_CPU_MASK_SIMPLE() at all for GICv3. i.e. > > > timer { > > compatible = "arm,armv8-timer"; > > interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > > <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > > <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > > <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; > > }; > > Please see the GICv3 binding documentation: > > Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > > ... and note that it does not have the cpumask field as use by the binding for > prior generations of GIC: > > Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml > > > If you've seen other dts files using GIC_CPU_MASK_SIMPLE() with GICv3, those > are incorrect, and need to be fixed. > > Thanks, > Mark. I'll use the bindings documentation as the primary reference. The use of GIC_CPU_MASK_SIMPLE() is removed and tests ok. These arm64 dts files in linux-next are gic-v3 and use GIC_CPU_MASK_SIMPLE(1, 2, 4, 8) ./nvidia/tegra234.dtsi ./renesas/r9a07g044.dtsi ./renesas/r8a779a0.dtsi ./qcom/sm8350.dtsi ./qcom/sm8250.dtsi ./freescale/fsl-ls1028a.dtsi ./freescale/imx8mp.dtsi ./freescale/imx8mn.dtsi ./freescale/imx8mm.dtsi Thanks, Brad
Hi Mark, On Fri, Nov 5, 2021 at 4:35 AM Marc Zyngier <maz@kernel.org> wrote: > > > > >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > > >> + > > > >> + gic_its: msi-controller@820000 { > > > >> + compatible = "arm,gic-v3-its"; > > > >> + msi-controller; > > > >> + #msi-cells = <1>; > > > >> + reg = <0x0 0x820000 0x0 0x10000>; > > > >> + socionext,synquacer-pre-its = > > > >> + <0xc00000 0x1000000>; > > > >> + }; > > > >> + }; > > > > > > > > Is there any shared lineage with Synquacer? The commit message didn't > > > > describe this quirk. > > > > > > Funny, it looks like there is a sudden outburst of stupid copy/paste > > > among HW designers. TI did the exact same thing recently. > > > > > > This totally negates all the advantages of having an ITS and makes > > > sure that you have all the overhead. Facepalm... > > > > Some background may help explain. To generate an LPI a peripheral must > > write to the GITS_TRANSLATER (a specific address). For the ITS to know > > which translations apply to the generated interrupts, it must know which > > peripheral performed the write. The ID of the peripheral is known as its > > DeviceID, which is often carried along with the write as an AXI sideband > > signal. > > Yes, I happen to be vaguely familiar with the GIC architecture. > > > The Elba SoC doesn't carry the DeviceID, so we have to conjure one up > > between the peripheral and the ITS. Instead of telling a peripheral to target > > the GITS_TRANSLATER directly, we instead direct it to a specific offset > > within a pre-ITS address range (our own IP block). For writes that land in > > that memory range, we derive the DeviceID from (offset >> 2). The pre-ITS > > block then sends (DeviceID, data) to the GITS_TRANSLATER. > > > > The hardware designer came up with the Pre-ITS mechanism in Feb 2018. > > When we looked at the upstream kernel later (we developed on 4.14) > > we found that not only did it support something similar, it supported the > > exact scheme we are using. > > And this scheme is totally wrong. It breaks interrupt isolation. > > Instead of having a single doorbell and getting the ITS to segregate > between devices itself, you end-up with multiple ones, allowing a > rogue device to impersonate another one by targeting another doorbell. > You can't even use an SMMU to preserve some isolation, because all the > doorbells are in the *same page*. Unmitigated disaster. > > At this stage, why did you bother having an ITS at all? You get none > of the security features. Only the excess area, memory allocation, > additional latency and complexity. All you get is a larger INTID > space. > > This only shows that the hardware designer didn't understand the ITS > at all. Which seems a common pattern, unfortunately. The Elba SoC is an embedded chip and not intended as a SBSA-compliant general platform. In this implementation the ITS is used to provide message-based interrupts for our (potentially large set) of hardware based platform device instances. Virtualization is not a consideration. We don't have a SMMU. Interrupt isolation isn't a practical consideration for this product. Propose adding a comment to the dts. + /* + * Elba SoC implemented a pre-ITS that happened to + * be the same implementation as synquacer. + */ its: interrupt-controller@820000 { compatible = "arm,gic-v3-its"; msi-controller; Thanks Brad
On Mon, 08 Nov 2021 19:35:14 +0000, Brad Larson <brad@pensando.io> wrote: > > Hi Mark, s/k/c/ > > On Fri, Nov 5, 2021 at 4:35 AM Marc Zyngier <maz@kernel.org> wrote: > > > > > > >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > > > >> + > > > > >> + gic_its: msi-controller@820000 { > > > > >> + compatible = "arm,gic-v3-its"; > > > > >> + msi-controller; > > > > >> + #msi-cells = <1>; > > > > >> + reg = <0x0 0x820000 0x0 0x10000>; > > > > >> + socionext,synquacer-pre-its = > > > > >> + <0xc00000 0x1000000>; > > > > >> + }; > > > > >> + }; > > > > > > > > > > Is there any shared lineage with Synquacer? The commit message didn't > > > > > describe this quirk. > > > > > > > > Funny, it looks like there is a sudden outburst of stupid copy/paste > > > > among HW designers. TI did the exact same thing recently. > > > > > > > > This totally negates all the advantages of having an ITS and makes > > > > sure that you have all the overhead. Facepalm... > > > > > > Some background may help explain. To generate an LPI a peripheral must > > > write to the GITS_TRANSLATER (a specific address). For the ITS to know > > > which translations apply to the generated interrupts, it must know which > > > peripheral performed the write. The ID of the peripheral is known as its > > > DeviceID, which is often carried along with the write as an AXI sideband > > > signal. > > > > Yes, I happen to be vaguely familiar with the GIC architecture. > > > > > The Elba SoC doesn't carry the DeviceID, so we have to conjure one up > > > between the peripheral and the ITS. Instead of telling a peripheral to target > > > the GITS_TRANSLATER directly, we instead direct it to a specific offset > > > within a pre-ITS address range (our own IP block). For writes that land in > > > that memory range, we derive the DeviceID from (offset >> 2). The pre-ITS > > > block then sends (DeviceID, data) to the GITS_TRANSLATER. > > > > > > The hardware designer came up with the Pre-ITS mechanism in Feb 2018. > > > When we looked at the upstream kernel later (we developed on 4.14) > > > we found that not only did it support something similar, it supported the > > > exact scheme we are using. > > > > And this scheme is totally wrong. It breaks interrupt isolation. > > > > Instead of having a single doorbell and getting the ITS to segregate > > between devices itself, you end-up with multiple ones, allowing a > > rogue device to impersonate another one by targeting another doorbell. > > You can't even use an SMMU to preserve some isolation, because all the > > doorbells are in the *same page*. Unmitigated disaster. > > > > At this stage, why did you bother having an ITS at all? You get none > > of the security features. Only the excess area, memory allocation, > > additional latency and complexity. All you get is a larger INTID > > space. > > > > This only shows that the hardware designer didn't understand the ITS > > at all. Which seems a common pattern, unfortunately. > > The Elba SoC is an embedded chip and not intended as a SBSA-compliant > general platform. This has nothing to do with following a standard. It has to do with following the intended use of the architecture. What you have here is the system architecture equivalent of trusting userspace to build the kernel page tables. It can work in limited cases. But would you want to deploy such construct at scale? Probably not. > In this implementation the ITS is used to provide message-based > interrupts for our (potentially large set) of hardware based > platform device instances. Virtualization is not a consideration. > We don't have a SMMU. Interrupt isolation isn't a practical > consideration for this product. Because you have foreseen all use cases for this HW ahead of time, and can already tell how SW is going to make use of it? Oh well... > Propose adding a comment to the dts. > > + /* > + * Elba SoC implemented a pre-ITS that happened to > + * be the same implementation as synquacer. > + */ Which contains zero information. What you really want is: "We have decided to ignore the system architecture, good luck". M.
On Mon, Nov 8, 2021 at 11:54 AM Marc Zyngier <maz@kernel.org> wrote: > > > > The Elba SoC is an embedded chip and not intended as a SBSA-compliant > > general platform. > > This has nothing to do with following a standard. It has to do with > following the intended use of the architecture. What you have here is > the system architecture equivalent of trusting userspace to build the > kernel page tables. It can work in limited cases. But would you want > to deploy such construct at scale? Probably not. > > > In this implementation the ITS is used to provide message-based > > interrupts for our (potentially large set) of hardware based > > platform device instances. Virtualization is not a consideration. > > We don't have a SMMU. Interrupt isolation isn't a practical > > consideration for this product. > > Because you have foreseen all use cases for this HW ahead of time, and > can already tell how SW is going to make use of it? Oh well... > > > Propose adding a comment to the dts. > > > > + /* > > + * Elba SoC implemented a pre-ITS that happened to > > + * be the same implementation as synquacer. > > + */ > > Which contains zero information. What you really want is: "We have > decided to ignore the system architecture, good luck". > > M. > > -- > Without deviation from the norm, progress is not possible. On the contrary, the confusion of using the existing driver match "socionext,synquacer-pre-its" is answered, why add new code. Looks like we are deviating from the norm ;-). I'm not seeing how this conversation is a productive use of time for a platform in production. Thanks, Brad
Hi Rob, On Wed, Oct 27, 2021 at 2:37 PM Rob Herring <robh@kernel.org> wrote: > > > +always-y := $(dtb-y) > > +subdir-y := $(dts-dirs) > > +clean-files := *.dtb > > None of these lines should be needed. Yes, these will be removed. > > diff --git a/arch/arm64/boot/dts/pensando/elba-16core.dtsi b/arch/arm64/boot/dts/pensando/elba-16core.dtsi > > new file mode 100644 > > index 000000000000..acf5941afbc1 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/pensando/elba-16core.dtsi > > @@ -0,0 +1,192 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > Do you care about using with non-GPL OS? Dual license is preferred. > Dual is fine, changing to this: SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > + psci { > > This goes at the root level. > Moving to the root level > > + compatible = "arm,psci-0.2"; > > + method = "smc"; > > + }; > > + > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi > > + > > +&spi0 { > > + num-cs = <4>; > > + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, > > + <&porta 7 GPIO_ACTIVE_LOW>; > > + status = "okay"; > > + spi0_cs0@0 { > > Node names should reflect the class of device and use standard name > defined in the DT spec. This probably doesn't have one. 'lora' perhaps? > Right, I didn't see a standard name and found many approaches in other files so I likely based off of one of these below. I searched the dts files for 'lora' and didn't find it. Is that an acronym? I can change it to what the preference is. ./microchip/sparx5_pcb134_board.dtsi: &spi0 { status = "okay"; spi@0 { compatible = "spi-mux"; ... }; ./rockchip/rk3399.dtsi: spi5 { spi5_clk: spi5-clk { rockchip,pins = <2 RK_PC6 2 &pcfg_pull_up>; }; spi5_cs0: spi5-cs0 { rockchip,pins = <2 RK_PC7 2 &pcfg_pull_up>; }; spi5_rx: spi5-rx { rockchip,pins = <2 RK_PC4 2 &pcfg_pull_up>; }; spi5_tx: spi5-tx { rockchip,pins = <2 RK_PC5 2 &pcfg_pull_up>; }; }; > > > + compatible = "semtech,sx1301"; /* Enable spidev */ > > What's spidev? > It's module drivers/spi/spidev.c which won't populate /dev/spidevB.C unless there is a match which we need for the system to boot. An earlier patch added to the compatible list below and the feedback on that was to remove it. Later I noticed the compatible list expanded... static const struct of_device_id spidev_dt_ids[] = { { .compatible = "rohm,dh2228fv" }, { .compatible = "lineartechnology,ltc2488" }, { .compatible = "semtech,sx1301" }, { .compatible = "lwn,bk4" }, { .compatible = "dh,dhcom-board" }, { .compatible = "menlo,m53cpld" }, { .compatible = "cisco,spi-petra" }, { .compatible = "micron,spi-authenta" }, {}, }; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + spi-max-frequency = <12000000>; > > + reg = <0>; > > + }; > > + > > + spi0_cs1@1 { > > + compatible = "semtech,sx1301"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + spi-max-frequency = <12000000>; > > + reg = <1>; > > + }; > > + > > + spi0_cs2@2 { > > + compatible = "semtech,sx1301"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + spi-max-frequency = <12000000>; > > + reg = <2>; > > + interrupt-parent = <&porta>; > > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > > + }; > > + > > + spi0_cs3@3 { > > + compatible = "semtech,sx1301"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + spi-max-frequency = <12000000>; > > + reg = <3>; > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/pensando/elba-asic.dts b/arch/arm64/boot/dts/pensando/elba-asic.dts > > new file mode 100644 > > index 000000000000..131931dc643f > > --- /dev/null > > +++ b/arch/arm64/boot/dts/pensando/elba-asic.dts > > @@ -0,0 +1,23 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > + > > +/dts-v1/; > > + > > +/ { > > + model = "Elba ASIC Board"; > > + compatible = "pensando,elba"; > > Normally we have a compatible for the board plus the soc compatible. In this case there are currently five different boards/products that have no variations needing a board level description. Thanks, Brad
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 639e01a4d855..34f99a99c488 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -20,6 +20,7 @@ subdir-y += marvell subdir-y += mediatek subdir-y += microchip subdir-y += nvidia +subdir-y += pensando subdir-y += qcom subdir-y += realtek subdir-y += renesas diff --git a/arch/arm64/boot/dts/pensando/Makefile b/arch/arm64/boot/dts/pensando/Makefile new file mode 100644 index 000000000000..61031ec11838 --- /dev/null +++ b/arch/arm64/boot/dts/pensando/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb + +always-y := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/pensando/elba-16core.dtsi b/arch/arm64/boot/dts/pensando/elba-16core.dtsi new file mode 100644 index 000000000000..acf5941afbc1 --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba-16core.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x0>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x1>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x2>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x3>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x200>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x201>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x202>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x203>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x300>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x301>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x302>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x303>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi new file mode 100644 index 000000000000..ba584c0fe0d5 --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2019-2021, Pensando Systems Inc. */ + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + num-cs = <4>; + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status = "okay"; + spi0_cs0@0 { + compatible = "semtech,sx1301"; /* Enable spidev */ + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12000000>; + reg = <0>; + }; + + spi0_cs1@1 { + compatible = "semtech,sx1301"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12000000>; + reg = <1>; + }; + + spi0_cs2@2 { + compatible = "semtech,sx1301"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12000000>; + reg = <2>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + spi0_cs3@3 { + compatible = "semtech,sx1301"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12000000>; + reg = <3>; + }; +}; diff --git a/arch/arm64/boot/dts/pensando/elba-asic.dts b/arch/arm64/boot/dts/pensando/elba-asic.dts new file mode 100644 index 000000000000..131931dc643f --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba-asic.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +/ { + model = "Elba ASIC Board"; + compatible = "pensando,elba"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" diff --git a/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi new file mode 100644 index 000000000000..e69734c2c267 --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "flash"; + reg = <0x10000 0xfff0000>; + }; + + partition@f0000 { + label = "golduenv"; + reg = <0xf0000 0x10000>; + }; + + partition@100000 { + label = "boot0"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "golduboot"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "brdcfg0"; + reg = <0x380000 0x10000>; + }; + + partition@390000 { + label = "brdcfg1"; + reg = <0x390000 0x10000>; + }; + + partition@400000 { + label = "goldfw"; + reg = <0x400000 0x3c00000>; + }; + + partition@4010000 { + label = "fwmap"; + reg = <0x4010000 0x20000>; + }; + + partition@4030000 { + label = "fwsel"; + reg = <0x4030000 0x20000>; + }; + + partition@4090000 { + label = "bootlog"; + reg = <0x4090000 0x20000>; + }; + + partition@40b0000 { + label = "panicbuf"; + reg = <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label = "uservars"; + reg = <0x40d0000 0x20000>; + }; + + partition@4200000 { + label = "uboota"; + reg = <0x4200000 0x400000>; + }; + + partition@4600000 { + label = "ubootb"; + reg = <0x4600000 0x400000>; + }; + + partition@4a00000 { + label = "mainfwa"; + reg = <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label = "mainfwb"; + reg = <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label = "diaguboot"; + reg = <0x6a00000 0x400000>; + }; + + partition@8000000 { + label = "diagfw"; + reg = <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label = "ubootenv"; + reg = <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/pensando/elba.dtsi b/arch/arm64/boot/dts/pensando/elba.dtsi new file mode 100644 index 000000000000..b28f69e0bd91 --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba.dtsi @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2019-2021, Pensando Systems Inc. */ + +#include <dt-bindings/gpio/gpio.h> +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + snps,sda-timeout-ms = <750>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + qspi: spi@2400 { + compatible = "pensando,elba-qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + spi0: spi@2800 { + compatible = "pensando,elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + pensando,spics = <&mssoc 0x2468>; + clocks = <&ahb_clk>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + status = "disabled"; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + uart0: serial@4800 { + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: msi-controller@820000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x820000 0x0 0x10000>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible = "pensando,elba-emmc", "cdns,sd4hc"; + clocks = <&emmc_clk>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + mmc-ddr-1_8v; + status = "disabled"; + }; + + mssoc: mssoc@307c0000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x307c0000 0x0 0x3000>; + }; + }; +};
Add Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson <brad@pensando.io> --- Changelog: - Node names changed to DT generic names - Changed from using 'spi@' which is reserved - The elba-flash-parts.dtsi is kept separate as it is included in multiple dts files. - SPDX license tags at the top of each file - The compatible = "pensando,elba" and 'model' are now together in the board file. - UIO nodes removed - Ordered nodes by increasing unit address - Removed an unreferenced container node. - Dropped deprecated 'device_type' for uart0 node. arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/pensando/Makefile | 6 + arch/arm64/boot/dts/pensando/elba-16core.dtsi | 192 ++++++++++++++++++ .../boot/dts/pensando/elba-asic-common.dtsi | 96 +++++++++ arch/arm64/boot/dts/pensando/elba-asic.dts | 23 +++ .../boot/dts/pensando/elba-flash-parts.dtsi | 103 ++++++++++ arch/arm64/boot/dts/pensando/elba.dtsi | 181 +++++++++++++++++ 7 files changed, 602 insertions(+) create mode 100644 arch/arm64/boot/dts/pensando/Makefile create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi