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Fri, 12 Nov 2021 08:31:22 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, aisheng.dong@nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de, ulf.hansson@linaro.org, broonie@kernel.org, linux@roeck-us.net, wim@linux-watchdog.org, linux@rempel-privat.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, daniel.lezcano@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-watchdog@vger.kernel.org, Jacky Bai , Peng Fan Subject: [PATCH V5 9/9] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Date: Fri, 12 Nov 2021 16:29:30 +0800 Message-Id: <20211112082930.3809351-10-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211112082930.3809351-1-peng.fan@oss.nxp.com> References: <20211112082930.3809351-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI2PR01CA0013.apcprd01.prod.exchangelabs.com (2603:1096:4:191::9) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SI2PR01CA0013.apcprd01.prod.exchangelabs.com (2603:1096:4:191::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4690.15 via Frontend Transport; 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Only the necessary devices for minimal system boot up are enabled: enet, emmc, usb, console uart. some of the devices' pin status may lost during low power mode, so additional sleep pinctrl properties are included by default. Reviewed-by: Dong Aisheng Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- - v4 Fix memory node Drop usb and fec nodes - v3 changes: no - v2 changes: add the memory node place holder update the license arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 80 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a14a6173b765..c64616192794 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts new file mode 100644 index 000000000000..b7cd4d28fee0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "NXP i.MX8ULP EVK"; + compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_enet: enetgrp { + fsl,pins = < + MX8ULP_PAD_PTE15__ENET0_MDC 0x43 + MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 + MX8ULP_PAD_PTE17__ENET0_RXER 0x43 + MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 + MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 + MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 + MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 + MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 + >; + }; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 + MX8ULP_PAD_PTD10__SDHC0_D0 0x43 + MX8ULP_PAD_PTD9__SDHC0_D1 0x43 + MX8ULP_PAD_PTD8__SDHC0_D2 0x43 + MX8ULP_PAD_PTD7__SDHC0_D3 0x43 + MX8ULP_PAD_PTD6__SDHC0_D4 0x43 + MX8ULP_PAD_PTD5__SDHC0_D5 0x43 + MX8ULP_PAD_PTD4__SDHC0_D6 0x43 + MX8ULP_PAD_PTD3__SDHC0_D7 0x43 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + >; + }; +};