| Message ID | 20211126163450.394861-2-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Stacked/parallel memories bindings | expand |
diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml index 8246891602e7..556c5ddc39d2 100644 --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml @@ -91,7 +91,7 @@ properties: - compatible patternProperties: - "^.*@[0-9a-f]+$": + "^.*@[0-9a-f]+,?[0-9a-f]*$": type: object properties:
The Xilinx QSPI controller has two advanced modes which allow the controller to behave differently and consider two flashes as one single storage. One of these two modes is quite complex to support from a binding point of view and is the dual parallel memories. In this mode, each byte of data is stored in both devices: the even bits in one, the odd bits in the other. The split is automatically handled by the QSPI controller and is transparent for the user. The other mode is simpler to support, it is called dual stacked memories. The controller shares the same SPI bus but each of the devices contain half of the data. Once in this mode, the controller does not follow CS requests but instead internally wires the two CSlevels with the value of the most significant address bit. Supporting these two modes will involve core changes which include the possibility of providing two CS for a single SPI device, and thus changing the node name regular expression. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- Documentation/devicetree/bindings/spi/spi-controller.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)