| Message ID | 20220104083631.40776-7-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | External ECC engines & Macronix support | expand |
On Tue, 4 Jan 2022 09:36:24 +0100 Miquel Raynal <miquel.raynal@bootlin.com> wrote: > Soon the SPI-NAND core will need a way to request a SPI controller to > enable ECC support for a given operation. This is because of the > pipelined integration of certain ECC engines, which are directly managed > by the SPI controller itself. > > Introduce a spi_mem_op additional field for this purpose: ecc. > > So far this field is left unset and checked to be false by all > the SPI controller drivers in their ->supports_op() hook, as they all > call spi_mem_default_supports_op(). > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > Acked-by: Pratyush Yadav <p.yadav@ti.com> > --- > drivers/spi/spi-mem.c | 5 +++++ > include/linux/spi/spi-mem.h | 5 +++++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c > index ed966d8129eb..f38ac31961c9 100644 > --- a/drivers/spi/spi-mem.c > +++ b/drivers/spi/spi-mem.c > @@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, > return false; > } > > + if (op->data.ecc) { > + if (!spi_mem_controller_is_capable(ctlr, ecc)) > + return false; > + } Nit: if (op->data.ecc && !spi_mem_controller_is_capable(ctlr, ecc)) return false; > + > return spi_mem_check_buswidth(mem, op); > } > EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); > diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h > index 4a1bfe689872..051050b40309 100644 > --- a/include/linux/spi/spi-mem.h > +++ b/include/linux/spi/spi-mem.h > @@ -89,6 +89,7 @@ enum spi_mem_data_dir { > * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not > * @data.buswidth: number of IO lanes used to send/receive the data > * @data.dtr: whether the data should be sent in DTR mode or not > + * @data.ecc: whether error correction is required or not > * @data.dir: direction of the transfer > * @data.nbytes: number of data bytes to send/receive. Can be zero if the > * operation does not involve transferring data > @@ -119,6 +120,7 @@ struct spi_mem_op { > struct { > u8 buswidth; > u8 dtr : 1; > + u8 ecc : 1; > enum spi_mem_data_dir dir; > unsigned int nbytes; > union { > @@ -126,6 +128,7 @@ struct spi_mem_op { > const void *out; > } buf; > } data; > + > }; > > #define SPI_MEM_OP(__cmd, __addr, __dummy, __data) \ > @@ -288,9 +291,11 @@ struct spi_controller_mem_ops { > /** > * struct spi_controller_mem_caps - SPI memory controller capabilities > * @dtr: Supports DTR operations > + * @ecc: Supports operations with error correction > */ > struct spi_controller_mem_caps { > bool dtr; > + bool ecc; > }; > > #define spi_mem_controller_is_capable(ctlr, cap) \
Hello Boris, boris.brezillon@collabora.com wrote on Tue, 4 Jan 2022 10:02:30 +0100: > On Tue, 4 Jan 2022 09:36:24 +0100 > Miquel Raynal <miquel.raynal@bootlin.com> wrote: > > > Soon the SPI-NAND core will need a way to request a SPI controller to > > enable ECC support for a given operation. This is because of the > > pipelined integration of certain ECC engines, which are directly managed > > by the SPI controller itself. > > > > Introduce a spi_mem_op additional field for this purpose: ecc. > > > > So far this field is left unset and checked to be false by all > > the SPI controller drivers in their ->supports_op() hook, as they all > > call spi_mem_default_supports_op(). > > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > > Acked-by: Pratyush Yadav <p.yadav@ti.com> > > --- > > drivers/spi/spi-mem.c | 5 +++++ > > include/linux/spi/spi-mem.h | 5 +++++ > > 2 files changed, 10 insertions(+) > > > > diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c > > index ed966d8129eb..f38ac31961c9 100644 > > --- a/drivers/spi/spi-mem.c > > +++ b/drivers/spi/spi-mem.c > > @@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, > > return false; > > } > > > > + if (op->data.ecc) { > > + if (!spi_mem_controller_is_capable(ctlr, ecc)) > > + return false; > > + } > > Nit: > > if (op->data.ecc && > !spi_mem_controller_is_capable(ctlr, ecc)) > return false; > Actually I wanted on purpose to distinguish the different checks: if (dtr) { do something here; } if (ecc) { do something else; } return; and in order to keep them tidy I used independent if statements within each of these :) > > + > > return spi_mem_check_buswidth(mem, op); > > } > > EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); > > diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h > > index 4a1bfe689872..051050b40309 100644 > > --- a/include/linux/spi/spi-mem.h > > +++ b/include/linux/spi/spi-mem.h > > @@ -89,6 +89,7 @@ enum spi_mem_data_dir { > > * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not > > * @data.buswidth: number of IO lanes used to send/receive the data > > * @data.dtr: whether the data should be sent in DTR mode or not > > + * @data.ecc: whether error correction is required or not > > * @data.dir: direction of the transfer > > * @data.nbytes: number of data bytes to send/receive. Can be zero if the > > * operation does not involve transferring data > > @@ -119,6 +120,7 @@ struct spi_mem_op { > > struct { > > u8 buswidth; > > u8 dtr : 1; > > + u8 ecc : 1; > > enum spi_mem_data_dir dir; > > unsigned int nbytes; > > union { > > @@ -126,6 +128,7 @@ struct spi_mem_op { > > const void *out; > > } buf; > > } data; > > + > > }; > > > > #define SPI_MEM_OP(__cmd, __addr, __dummy, __data) \ > > @@ -288,9 +291,11 @@ struct spi_controller_mem_ops { > > /** > > * struct spi_controller_mem_caps - SPI memory controller capabilities > > * @dtr: Supports DTR operations > > + * @ecc: Supports operations with error correction > > */ > > struct spi_controller_mem_caps { > > bool dtr; > > + bool ecc; > > }; > > > > #define spi_mem_controller_is_capable(ctlr, cap) \ > Thanks, Miquèl
On Tue, 2022-01-04 at 08:36:24 UTC, Miquel Raynal wrote: > Soon the SPI-NAND core will need a way to request a SPI controller to > enable ECC support for a given operation. This is because of the > pipelined integration of certain ECC engines, which are directly managed > by the SPI controller itself. > > Introduce a spi_mem_op additional field for this purpose: ecc. > > So far this field is left unset and checked to be false by all > the SPI controller drivers in their ->supports_op() hook, as they all > call spi_mem_default_supports_op(). > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > Acked-by: Pratyush Yadav <p.yadav@ti.com> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-mem-ecc. Miquel
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index ed966d8129eb..f38ac31961c9 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, return false; } + if (op->data.ecc) { + if (!spi_mem_controller_is_capable(ctlr, ecc)) + return false; + } + return spi_mem_check_buswidth(mem, op); } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 4a1bfe689872..051050b40309 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -89,6 +89,7 @@ enum spi_mem_data_dir { * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data * @data.dtr: whether the data should be sent in DTR mode or not + * @data.ecc: whether error correction is required or not * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the * operation does not involve transferring data @@ -119,6 +120,7 @@ struct spi_mem_op { struct { u8 buswidth; u8 dtr : 1; + u8 ecc : 1; enum spi_mem_data_dir dir; unsigned int nbytes; union { @@ -126,6 +128,7 @@ struct spi_mem_op { const void *out; } buf; } data; + }; #define SPI_MEM_OP(__cmd, __addr, __dummy, __data) \ @@ -288,9 +291,11 @@ struct spi_controller_mem_ops { /** * struct spi_controller_mem_caps - SPI memory controller capabilities * @dtr: Supports DTR operations + * @ecc: Supports operations with error correction */ struct spi_controller_mem_caps { bool dtr; + bool ecc; }; #define spi_mem_controller_is_capable(ctlr, cap) \