| Message ID | 20220719144906.382548-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | None | expand |
Hi All, I would like to drop this patch as I have sent wrong one. Cheers, Biju > Subject: [PATCH 2/2] spi: spi-rspi: Add need_dmar_clr to spi_ops > > RSPI IP on RZ/{A, G2L} SoC's has the same signal for both interrupt and DMA > transfer request. Setting DMARS register for DMA transfer makes the signal > to work as a DMA transfer request signal and subsequent interrupt requests > to the interrupt controller are masked. > > Currently, DMA to interrupt mode switching does not work because of this > masking. > > This patch adds need_dmar_clr device configuration flag to spi_ops and it > makes the signal to work as an interrupt request by clearing DMARS after DMA > callback. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > drivers/spi/spi-rspi.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index > 7a014eeec2d0..8637be53bb8d 100644 > --- a/drivers/spi/spi-rspi.c > +++ b/drivers/spi/spi-rspi.c > @@ -249,6 +249,7 @@ struct spi_ops { > u16 flags; > u16 fifo_size; > u8 num_hw_ss; > + bool need_dmar_clr; > }; > > static void rspi_set_rate(struct rspi_data *rspi) @@ -613,6 +614,12 @@ > static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, > rspi->dma_callbacked, HZ); > if (ret > 0 && rspi->dma_callbacked) { > ret = 0; > + if (need_dmar_clr) { > + if (tx) > + dmaengine_synchronize(rspi->ctlr->dma_tx); > + if (rx) > + dmaengine_synchronize(rspi->ctlr->dma_rx); > + } > } else { > if (!ret) { > dev_err(&rspi->ctlr->dev, "DMA timeout\n"); @@ -1196,6 > +1203,7 @@ static const struct spi_ops rspi_rz_ops = { > .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, > .fifo_size = 8, /* 8 for TX, 32 for RX */ > .num_hw_ss = 1, > + .need_dmar_clr = true, > }; > > static const struct spi_ops qspi_ops = { > -- > 2.25.1
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 7a014eeec2d0..8637be53bb8d 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -249,6 +249,7 @@ struct spi_ops { u16 flags; u16 fifo_size; u8 num_hw_ss; + bool need_dmar_clr; }; static void rspi_set_rate(struct rspi_data *rspi) @@ -613,6 +614,12 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, rspi->dma_callbacked, HZ); if (ret > 0 && rspi->dma_callbacked) { ret = 0; + if (need_dmar_clr) { + if (tx) + dmaengine_synchronize(rspi->ctlr->dma_tx); + if (rx) + dmaengine_synchronize(rspi->ctlr->dma_rx); + } } else { if (!ret) { dev_err(&rspi->ctlr->dev, "DMA timeout\n"); @@ -1196,6 +1203,7 @@ static const struct spi_ops rspi_rz_ops = { .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, .fifo_size = 8, /* 8 for TX, 32 for RX */ .num_hw_ss = 1, + .need_dmar_clr = true, }; static const struct spi_ops qspi_ops = {
RSPI IP on RZ/{A, G2L} SoC's has the same signal for both interrupt and DMA transfer request. Setting DMARS register for DMA transfer makes the signal to work as a DMA transfer request signal and subsequent interrupt requests to the interrupt controller are masked. Currently, DMA to interrupt mode switching does not work because of this masking. This patch adds need_dmar_clr device configuration flag to spi_ops and it makes the signal to work as an interrupt request by clearing DMARS after DMA callback. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/spi/spi-rspi.c | 8 ++++++++ 1 file changed, 8 insertions(+)