| Message ID | 20220810085914.801170-1-conor.dooley@microchip.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 7eac0081a8e958106ed3aea402c8105f30fad6d9 |
| Headers | show |
| Series | riscv: dts: microchip: add qspi compatible fallback | expand |
On 10/08/2022 11:59, Conor Dooley wrote: > The "hard" QSPI peripheral on PolarFire SoC is derived from version 2 > of the FPGA IP core. The original binding had no fallback etc, so this > device tree is valid as is. There was also no functional driver for the > QSPI IP, so no device with a devicetree from a previous mainline > release will regress. > > Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/ > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > See the link for binding discussion. I'll apply this at some point once Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
From: Conor Dooley <conor.dooley@microchip.com> On Wed, 10 Aug 2022 09:59:15 +0100, Conor Dooley wrote: > The "hard" QSPI peripheral on PolarFire SoC is derived from version 2 > of the FPGA IP core. The original binding had no fallback etc, so this > device tree is valid as is. There was also no functional driver for the > QSPI IP, so no device with a devicetree from a previous mainline > release will regress. > > > [...] Applied to dt-for-next, thanks! [1/1] riscv: dts: microchip: add qspi compatible fallback https://git.kernel.org/conor/c/7eac0081a8e9 Thanks, Conor.
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 499c2e63ad35..45e3cc659882 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -330,7 +330,7 @@ spi1: spi@20109000 { }; qspi: spi@21000000 { - compatible = "microchip,mpfs-qspi"; + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21000000 0x0 0x1000>;
The "hard" QSPI peripheral on PolarFire SoC is derived from version 2 of the FPGA IP core. The original binding had no fallback etc, so this device tree is valid as is. There was also no functional driver for the QSPI IP, so no device with a devicetree from a previous mainline release will regress. Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- See the link for binding discussion. I'll apply this at some point once the driver makes it upstream. CC: nagasuresh.relli@microchip.com CC: valentina.fernandezalanis@microchip.com CC: broonie@kernel.org CC: devicetree@vger.kernel.org CC: krzysztof.kozlowski+dt@linaro.org CC: robh+dt@kernel.org CC: linux-kernel@vger.kernel.org CC: linux-spi@vger.kernel.org CC: linux-riscv@lists.infradead.org --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)