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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2023 15:50:13.7492 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ca6ab6c-dbb9-43f1-b0e9-08db167ed175 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7729 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Tegra QSPI controller only supports half duplex transfers. Set half duplex constrain flag. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 39dec2dc161b..fe15fa6eecd1 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1553,6 +1553,7 @@ static int tegra_qspi_probe(struct platform_device *pdev) master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH | SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); + master->flags = SPI_CONTROLLER_HALF_DUPLEX; master->setup = tegra_qspi_setup; master->transfer_one_message = tegra_qspi_transfer_one_message; master->num_chipselect = 1;