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Wed, 22 Mar 2023 09:02:59 +0000 From: haibo.chen@nxp.com To: broonie@kernel.org, han.xu@nxp.com Cc: linux-spi@vger.kernel.org, yogeshgaur.83@gmail.com, haibo.chen@nxp.com, linux-imx@nxp.com Subject: [PATCH 2/2] spi: spi-nxp-fspi: use DLL calibration when clock rate > 100MHz Date: Wed, 22 Mar 2023 17:04:51 +0800 Message-Id: <20230322090451.3179431-2-haibo.chen@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230322090451.3179431-1-haibo.chen@nxp.com> References: <20230322090451.3179431-1-haibo.chen@nxp.com> X-ClientProxiedBy: SI2PR04CA0007.apcprd04.prod.outlook.com (2603:1096:4:197::19) To DB7PR04MB4010.eurprd04.prod.outlook.com (2603:10a6:5:21::30) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB7PR04MB4010:EE_|DB9PR04MB8123:EE_ X-MS-Office365-Filtering-Correlation-Id: e94fe5f7-eac6-42a0-691c-08db2ab43be5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4Wz+raWEGPMPZiEag64Ze+c7vC8VnWVI7xEgsLhU4iJOPMzOHW4lb6OtHg6pgNdmMtb5vkU9FgoWDLGRX3DdCyrJ7fKv6E3LXHOPrmnTcI47+iwuDuyokhwaoIsp0Ui2zrK/h1OD9edEiQSYT+nfdTB3d6dyBa+pQ6iO4x7/I8BP55iIMlcz3qjYX/CS1Tfv6TujcP9XL7u792mBPPJVeI8Cmq9MBBvogj8Yd03PUeR2ZuB64BgDLzS8wCpAAyJgQt0Amh9VQxOCdrUJyDJddq4vxFMnHRsnVSjxLe3LwgEFA5GQSU9Zh7tMXkCAyei2j9BVL2J+7rJREQu9YAtpUh0e332GNSCTHJGn6ajesTgYY5yDIhAius7PS1YLSlNKpSnNG/46zKbsOqx6epdp3YZjB8GG/H0m7RjUwDxr1d4yATUDhEb+ANlizXbuQSchQGqCdNUZTgP3K+ASDnfKKfT6YqvpfRjt5/TtjNw1odk5qCjrVphC8KImdFiZko61bwq9VsQD6GZGk1vbZ4DBpAsRnlbAlIOBs+LosaFj54HJ692Vpfm6Q1/5cfzQmNsBekX8qAuazsz2sR8HYG4+z4N3tLeKVZf/KdWmNTabL7eUaQoYLxEGjPaL6SumWuMYhHgkIbDP8zYbfcKotuXHtgF5mhPYZKEnWyHgJCOt5ORjhgcNwBby4jphlh/vuwI0T/zDqJN1FnuYPi0sOwXl0w== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB7PR04MB4010.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(4636009)(376002)(39860400002)(396003)(136003)(366004)(346002)(451199018)(38100700002)(38350700002)(86362001)(36756003)(66476007)(66946007)(66556008)(8936002)(186003)(8676002)(6512007)(6486002)(6666004)(41300700001)(1076003)(9686003)(4326008)(478600001)(6506007)(316002)(26005)(52116002)(2906002)(2616005)(83380400001)(5660300002);DIR:OUT;SFP:1101; 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Signed-off-by: Haibo Chen Reviewed-by: Han Xu Tested-by: Han Xu --- drivers/spi/spi-nxp-fspi.c | 52 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 6735c22b9137..544017655787 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -214,9 +214,15 @@ #define FSPI_DLLACR 0xC0 #define FSPI_DLLACR_OVRDEN BIT(8) +#define FSPI_DLLACR_SLVDLY(x) ((x) << 3) +#define FSPI_DLLACR_DLLRESET BIT(1) +#define FSPI_DLLACR_DLLEN BIT(0) #define FSPI_DLLBCR 0xC4 #define FSPI_DLLBCR_OVRDEN BIT(8) +#define FSPI_DLLBCR_SLVDLY(x) ((x) << 3) +#define FSPI_DLLBCR_DLLRESET BIT(1) +#define FSPI_DLLBCR_DLLEN BIT(0) #define FSPI_STS0 0xE0 #define FSPI_STS0_DLPHB(x) ((x) << 8) @@ -231,6 +237,16 @@ #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) #define FSPI_STS1_AHB_ERRID(x) (x) +#define FSPI_STS2 0xE8 +#define FSPI_STS2_BREFLOCK BIT(17) +#define FSPI_STS2_BSLVLOCK BIT(16) +#define FSPI_STS2_AREFLOCK BIT(1) +#define FSPI_STS2_ASLVLOCK BIT(0) +#define FSPI_STS2_AB_LOCK (FSPI_STS2_BREFLOCK | \ + FSPI_STS2_BSLVLOCK | \ + FSPI_STS2_AREFLOCK | \ + FSPI_STS2_ASLVLOCK) + #define FSPI_AHBSPNST 0xEC #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) @@ -615,6 +631,35 @@ static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) return 0; } +static void nxp_fspi_dll_calibration(struct nxp_fspi *f) +{ + int ret; + + /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */ + fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR); + fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR); + fspi_writel(f, 0, f->iobase + FSPI_DLLACR); + fspi_writel(f, 0, f->iobase + FSPI_DLLBCR); + + /* + * Enable the DLL calibration mode. + * The delay target for slave delay line is: + * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock. + * When clock rate > 100MHz, recommend SLVDLYTARGET is 0xF, which + * means half of clock cycle of reference clock. + */ + fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(0xF), + f->iobase + FSPI_DLLACR); + fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(0xF), + f->iobase + FSPI_DLLBCR); + + /* Wait to get REF/SLV lock */ + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK, + 0, POLL_TOUT, true); + if (ret) + dev_warn(f->dev, "DLL lock failed, please fix it!\n"); +} + /* * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 * register and start base address of the slave device. @@ -690,6 +735,13 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) if (ret) return; + /* + * If clock rate > 100MHz, then switch from DLL override mode to + * DLL calibration mode. + */ + if (rate > 100000000) + nxp_fspi_dll_calibration(f); + f->selected = spi_get_chipselect(spi, 0); }