| Message ID | 20240201094353.33281-4-jaimeliao.tw@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add octal DTR support for Macronix flash | expand |
> From: JaimeLiao <jaimeliao@mxic.com.tw> Same remark as for patch 2/9. > Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. > The byte order of 16-bit words is swapped when read or written in > 8D-8D-8D > mode compared to STR modes. Allow operations to specify the byte order > in > DTR mode, so that controllers can swap the bytes back at run-time to > address the flash's endianness requirements, if they are capable. If > the > controllers are not capable of swapping the bytes, the protocol is > downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the > swapping > of the bytes is always done regardless if it's a data or register > access, > so that we comply with the JESD216 requirements: "Byte order of 16-bit > words is swapped when read in 8D-8D-8D mode compared to 1-1-1". > > Merge Tudor's patch and add modifications for suiting newer version > of Linux kernel. > > Suggested-by: Michael Walle <mwalle@kernel.org> > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> > --- > drivers/mtd/spi-nor/core.c | 5 +++++ > drivers/mtd/spi-nor/core.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 4129764fad8c..0076007e1cde 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -113,6 +113,11 @@ void spi_nor_spimem_setup_op(const struct spi_nor > *nor, > op->cmd.opcode = (op->cmd.opcode << 8) | ext; > op->cmd.nbytes = 2; > } > + > + /* SWAP16 is only applicable when Octal DTR mode */ > + if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) Why is it read_proto now? For all the former patches, the local proto variable was used. > + if (nor->flags & SNOR_F_SWAP16) Please fold this into the former condition. if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16) op->data.swap16 = true; -michael > + op->data.swap16 = true; > } > > /** > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index d36c0e072954..3c5190ac0a79 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -140,6 +140,7 @@ enum spi_nor_option_flags { > SNOR_F_RWW = BIT(14), > SNOR_F_ECC = BIT(15), > SNOR_F_NO_WP = BIT(16), > + SNOR_F_SWAP16 = BIT(17), > }; > > struct spi_nor_read_command {
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 4129764fad8c..0076007e1cde 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -113,6 +113,11 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, op->cmd.opcode = (op->cmd.opcode << 8) | ext; op->cmd.nbytes = 2; } + + /* SWAP16 is only applicable when Octal DTR mode */ + if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) + if (nor->flags & SNOR_F_SWAP16) + op->data.swap16 = true; } /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index d36c0e072954..3c5190ac0a79 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -140,6 +140,7 @@ enum spi_nor_option_flags { SNOR_F_RWW = BIT(14), SNOR_F_ECC = BIT(15), SNOR_F_NO_WP = BIT(16), + SNOR_F_SWAP16 = BIT(17), }; struct spi_nor_read_command {