| Message ID | 20240201094353.33281-6-jaimeliao.tw@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add octal DTR support for Macronix flash | expand |
On Thu, Feb 01, 2024 at 05:43:49PM +0800, Jaime Liao wrote: > From: JaimeLiao <jaimeliao@mxic.com.tw> > > Some SPI-NOR flash swap the bytes on a 16-bit boundary when > configured in Octal DTR mode. It means data format D0 D1 D2 D3 > would be swapped to D1 D0 D3 D2. So that whether controller > support swapping bytes should be checked before enable Octal > DTR mode. Add swap byte support on a 16-bit boundary when > configured in Octal DTR mode for Macronix xSPI host controller > dirver. Acked-by: Mark Brown <broonie@kernel.org>
Hi, > From: JaimeLiao <jaimeliao@mxic.com.tw> > > Some SPI-NOR flash swap the bytes on a 16-bit boundary when > configured in Octal DTR mode. It means data format D0 D1 D2 D3 > would be swapped to D1 D0 D3 D2. So that whether controller > support swapping bytes should be checked before enable Octal > DTR mode. Add swap byte support on a 16-bit boundary when > configured in Octal DTR mode for Macronix xSPI host controller > dirver. > > According dtr_swab in operation to enable/disable Macronix > xSPI host controller swap byte feature. > > To make sure swap byte feature is working well, program data in > 1S-1S-1S mode then read back and compare read data in 8D-8D-8D > mode. > > This feature have been validated on byte-swap flash and > non-byte-swap flash. > > Macronix xSPI host controller bit "HC_CFG_DATA_PASS" determine > the byte swap feature disabled/enabled and swap byte feature is > working on 8D-8D-8D mode only. > > Suggested-by: Michael Walle <mwalle@kernel.org> > Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> > --- > drivers/spi/spi-mxic.c | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c > index 60c9f3048ac9..8ac302e48c9f 100644 > --- a/drivers/spi/spi-mxic.c > +++ b/drivers/spi/spi-mxic.c > @@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) > mxic->regs + HC_CFG); > } > > -static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) > +static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags, > + bool swap16) > { > int nio = 1; > > @@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device > *spi, u32 flags) > else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) > nio = 2; > > + if (!swap16) > + flags |= HC_CFG_DATA_PASS; > + else > + flags &= ~HC_CFG_DATA_PASS; Again, not my driver and I don't care too much, but you are changing the behavior of this driver. If I had to guess, with this patch applied, you'd read data (in octal mode) with the bytes swapped compared to kernel without this patch. And compared to the former version, you just made it harder to read by using negated logic. -michael > + > return flags | HC_CFG_NIO(nio) | > HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) | > HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | > HC_CFG_IDLE_SIO_LVL(1); > @@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct > spi_mem_dirmap_desc *desc, > if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) > return -EINVAL; > > - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); > + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, > desc->info.op_tmpl.data.swap16), > + mxic->regs + HC_CFG); > > writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), > mxic->regs + LRD_CFG); > @@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct > spi_mem_dirmap_desc *desc, > if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) > return -EINVAL; > > - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); > + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, > desc->info.op_tmpl.data.swap16), > + mxic->regs + HC_CFG); > > writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), > mxic->regs + LWR_CFG); > @@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem > *mem, > if (ret) > return ret; > > - writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN), > + writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, > op->data.swap16), > mxic->regs + HC_CFG); > > writel(HC_EN_BIT, mxic->regs + HC_EN); > @@ -572,6 +580,7 @@ static const struct spi_controller_mem_ops > mxic_spi_mem_ops = { > > static const struct spi_controller_mem_caps mxic_spi_mem_caps = { > .dtr = true, > + .swap16 = true, > .ecc = true, > };
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 60c9f3048ac9..8ac302e48c9f 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) mxic->regs + HC_CFG); } -static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) +static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags, + bool swap16) { int nio = 1; @@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) nio = 2; + if (!swap16) + flags |= HC_CFG_DATA_PASS; + else + flags &= ~HC_CFG_DATA_PASS; + return flags | HC_CFG_NIO(nio) | HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) | HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1); @@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) return -EINVAL; - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16), + mxic->regs + HC_CFG); writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), mxic->regs + LRD_CFG); @@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) return -EINVAL; - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16), + mxic->regs + HC_CFG); writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), mxic->regs + LWR_CFG); @@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, if (ret) return ret; - writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN), + writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16), mxic->regs + HC_CFG); writel(HC_EN_BIT, mxic->regs + HC_EN); @@ -572,6 +580,7 @@ static const struct spi_controller_mem_ops mxic_spi_mem_ops = { static const struct spi_controller_mem_caps mxic_spi_mem_caps = { .dtr = true, + .swap16 = true, .ecc = true, };