| Message ID | 20240201094353.33281-7-jaimeliao.tw@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add octal DTR support for Macronix flash | expand |
Hi, > From: JaimeLiao <jaimeliao@mxic.com.tw> > > Adding Macronix Octal flash for Octal DTR support. > > The octaflash series can be divided into the following types: > > MX25 series : Serial NOR Flash. > LM/UM series : Up to 250MHz clock frequency with both DTR/STR > operation. > LW/UW series : Support simultaneous Read-while-Write operation in > multiple > bank architecture. Read-while-write feature which means > read > data one bank while another bank is programing or > erasing. > > MX25LW : 3.0V Octal I/O with Read-while-Write > MX25UW : 1.8V Octal I/O with Read-while-Write > > MX25LM : 3.0V Octal I/O > Link: > https://www.mxic.com.tw/Lists/Datasheet/Attachments/8729/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf > > MX25UM : 1.8V Octal I/O > Link: > https://www.mxic.com.tw/Lists/Datasheet/Attachments/8967/MX25UM51245G,%201.8V,%20512Mb,%20v1.5.pdf > > Those flash have been tested on Xilinx Zynq-picozed board using > MXIC SPI controller. > As below are debugfs data, the SFDP table and result of mtd-utils > tests dump. > > --- What is this? There is already a "---" below. It goes like this: [From:] Patch description. Link: Link: Signed-off-by: --- Test data and SFDP dump diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c ... -michael
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index dee71776b1a8..467bb5c97d6c 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -200,6 +200,46 @@ static const struct flash_info macronix_nor_parts[] = { .name = "mx25l3255e", .size = SZ_4M, .no_sfdp_flags = SECT_4K, + }, { + .id = SNOR_ID(0xc2, 0x84, 0x37), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x81, 0x37), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x84, 0x38), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x81, 0x38), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x84, 0x39), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x81, 0x39), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x86, 0x39), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x84, 0x3a), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x86, 0x3a), + .n_banks = 4, + .flags = SPI_NOR_RWW, + }, { + .id = SNOR_ID(0xc2, 0x84, 0x3b), + .n_banks = 4, + .flags = SPI_NOR_RWW, } };