| Message ID | 20240207111516.2563218-3-tudor.ambarus@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 80d3204a3b1dbef570ed29d4d375e4d6922da82d |
| Headers | show |
| Series | spi: s3c64xx: add support for google,gs101-spi | expand |
On Wed, Feb 7, 2024 at 5:15 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > There are SoCs (gs101) that allow only 32 bit register accesses. As the > requirement is rare enough, for those SoCs we'll open code in the driver > some s3c64xx_iowrite{8,16}_32_rep() accessors. Prepare for such addition. > > Suggested-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > drivers/spi/spi-s3c64xx.c | 35 +++++++++++++++++++++-------------- > 1 file changed, 21 insertions(+), 14 deletions(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index 7f7eb8f742e4..eb79c6e4f509 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -414,6 +414,26 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, > > } > > +static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, > + struct spi_transfer *xfer) > +{ > + void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA; > + const void *buf = xfer->tx_buf; > + unsigned int len = xfer->len; > + > + switch (sdd->cur_bpw) { > + case 32: > + iowrite32_rep(addr, buf, len / 4); > + break; > + case 16: > + iowrite16_rep(addr, buf, len / 2); > + break; > + default: > + iowrite8_rep(addr, buf, len); > + break; > + } > +} > + > static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, > struct spi_transfer *xfer, int dma_mode) > { > @@ -447,20 +467,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, > modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; > ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); > } else { > - switch (sdd->cur_bpw) { > - case 32: > - iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, > - xfer->tx_buf, xfer->len / 4); > - break; > - case 16: > - iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, > - xfer->tx_buf, xfer->len / 2); > - break; > - default: > - iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, > - xfer->tx_buf, xfer->len); > - break; > - } > + s3c64xx_iowrite_rep(sdd, xfer); > } > } > > -- > 2.43.0.687.g38aa6559b0-goog >
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 7f7eb8f742e4..eb79c6e4f509 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -414,6 +414,26 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, } +static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, + struct spi_transfer *xfer) +{ + void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA; + const void *buf = xfer->tx_buf; + unsigned int len = xfer->len; + + switch (sdd->cur_bpw) { + case 32: + iowrite32_rep(addr, buf, len / 4); + break; + case 16: + iowrite16_rep(addr, buf, len / 2); + break; + default: + iowrite8_rep(addr, buf, len); + break; + } +} + static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer, int dma_mode) { @@ -447,20 +467,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); } else { - switch (sdd->cur_bpw) { - case 32: - iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len / 4); - break; - case 16: - iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len / 2); - break; - default: - iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len); - break; - } + s3c64xx_iowrite_rep(sdd, xfer); } }
There are SoCs (gs101) that allow only 32 bit register accesses. As the requirement is rare enough, for those SoCs we'll open code in the driver some s3c64xx_iowrite{8,16}_32_rep() accessors. Prepare for such addition. Suggested-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- drivers/spi/spi-s3c64xx.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-)