From patchwork Mon Jul 29 08:43:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 13744602 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44AD413C8EA for ; Mon, 29 Jul 2024 08:52:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722243173; cv=none; b=EBpgUlCIJDe7nM2wryyHNEHmLoZd7z7h7YVITrZWM4jRePlJgft9IoQiYIAhaIEPMpVmhj/xpVTbaVsB07Bagb/AMFm/qbJJQE+uLm3EiIuOc/yaP/BdpC22oib7HkWVUHYkw/F8dieTFOjUP3GS0KVY5An6a4s7Yuak49l4dJI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722243173; c=relaxed/simple; bh=90BRJBj1CM6mY+PLAgwMNXPd/8hj3aTG3H1cqACxXwU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=o4/SY6NgE3DVzRSgdRI0fPGCeHKGWUnKUF5gl+URHUJMJMNScu0Vrbat6qy781LRXUOW+TKGiYRbhxVPSbfeIsDSzjG2b5ih7wheUPiFQEJ9BH0btH+KvjB4PedYkAfwOG4h4XNEr4CD0Wjz7GDjrILg/MgPo/ttbIuL45BOT2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B1IbGZeo; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B1IbGZeo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722243172; x=1753779172; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=90BRJBj1CM6mY+PLAgwMNXPd/8hj3aTG3H1cqACxXwU=; b=B1IbGZeoG2z1dwmX4qd7pwPWyQYYV/alLCMQOQPTwSxqGaQz8ba2MLJR FHu+7LPCyDOCA6leufWmMVVogBFnkZBlcOcZveOgjRlHcIOJs7D2TvFeU XeAATFU0gKKaFKfJfsxtUNnkZUzVfG46zVMLlE9FdV3OqtgF1bNvvI4qc trwmCQcl3tw8MwTZUCKPYs9D9wap+R4G5e4CZROYiQlGvH566qq5R1EaU 7Rg6WMdqyoh5zMs7hBpanXZ36GbsPjJHRkylvJRHjZv84hfUPdpqYGOjs 2me/j+kvAbdbj5+zu5qGou+Vz1T4HXgwHUMh63oUObt9NWfl7jP0Lgfh3 A==; X-CSE-ConnectionGUID: HpJka8Q4QiqqmpRp6xrUQQ== X-CSE-MsgGUID: OemOox1NTTiBfn/pSbIwcA== X-IronPort-AV: E=McAfee;i="6700,10204,11147"; a="42509150" X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="42509150" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2024 01:52:52 -0700 X-CSE-ConnectionGUID: aAvyOwOjTAaj4VQMclXuMg== X-CSE-MsgGUID: sRyx8ayaQQ2E8ItZ7ZLzow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="54708800" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2024 01:52:47 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v5 12/12] drm/xe/spi: add support for access mode Date: Mon, 29 Jul 2024 11:43:26 +0300 Message-Id: <20240729084326.2278014-13-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729084326.2278014-1-alexander.usyskin@intel.com> References: <20240729084326.2278014-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Check SPI access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 ++++ drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +--- drivers/gpu/drm/xe/xe_spi.c | 33 ++++++++++++++++++++++++++- 3 files changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h index e2a925be137c..e22082875811 100644 --- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h @@ -16,6 +16,10 @@ #define MTL_GSC_HECI1_BASE 0x00116000 #define MTL_GSC_HECI2_BASE 0x00117000 +#define DG1_GSC_HECI2_BASE 0x00259000 +#define PVC_GSC_HECI2_BASE 0x00285000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define HECI_H_CSR(base) XE_REG((base) + 0x4) #define HECI_H_CSR_IE REG_BIT(0) #define HECI_H_CSR_IS REG_BIT(1) diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c index 65b2e147c4b9..27734085164e 100644 --- a/drivers/gpu/drm/xe/xe_heci_gsc.c +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c @@ -11,14 +11,11 @@ #include "xe_device_types.h" #include "xe_drv.h" #include "xe_heci_gsc.h" +#include "regs/xe_gsc_regs.h" #include "xe_platform_types.h" #define GSC_BAR_LENGTH 0x00000FFC -#define DG1_GSC_HECI2_BASE 0x259000 -#define PVC_GSC_HECI2_BASE 0x285000 -#define DG2_GSC_HECI2_BASE 0x374000 - static void heci_gsc_irq_mask(struct irq_data *d) { /* generic irq handling */ diff --git a/drivers/gpu/drm/xe/xe_spi.c b/drivers/gpu/drm/xe/xe_spi.c index 37080b82e9ae..47341418f772 100644 --- a/drivers/gpu/drm/xe/xe_spi.c +++ b/drivers/gpu/drm/xe/xe_spi.c @@ -5,7 +5,10 @@ #include #include +#include "xe_device.h" #include "xe_device_types.h" +#include "xe_mmio.h" +#include "regs/xe_gsc_regs.h" #include "xe_spi.h" #include "xe_sriov.h" @@ -24,6 +27,34 @@ static void xe_spi_release_dev(struct device *dev) { } +static bool xe_spi_writeable_override(struct xe_device *xe) +{ + struct xe_gt *gt = xe_root_mmio_gt(xe); + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); + resource_size_t base; + bool writeable_override; + + if (xe->info.platform == XE_BATTLEMAGE) { + base = DG2_GSC_HECI2_BASE; + } else if (xe->info.platform == XE_PVC) { + base = PVC_GSC_HECI2_BASE; + } else if (xe->info.platform == XE_DG2) { + base = DG2_GSC_HECI2_BASE; + } else if (xe->info.platform == XE_DG1) { + base = DG1_GSC_HECI2_BASE; + } else { + dev_err(&pdev->dev, "Unknown platform\n"); + return true; + } + + writeable_override = + !(xe_mmio_read32(gt, HECI_H_GS1(base)) & + HECI_FW_STATUS_2_SPI_ACCESS_MODE); + if (writeable_override) + dev_info(&pdev->dev, "SPI access overridden by jumper\n"); + return writeable_override; +} + void xe_spi_init(struct xe_device *xe) { struct intel_dg_spi_dev *spi = &xe->spi; @@ -38,7 +69,7 @@ void xe_spi_init(struct xe_device *xe) if (IS_SRIOV_VF(xe)) return; - spi->writeable_override = false; + spi->writeable_override = xe_spi_writeable_override(xe); spi->bar.parent = &pdev->resource[0]; spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start; spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;