From patchwork Mon Sep 16 13:49:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 13805514 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C557158A30 for ; Mon, 16 Sep 2024 13:57:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495078; cv=none; b=g57YeWpPYFfRkm8zfrJC2a1Lq7QXqU85Fd1kuC0uNHCsG5EAQg7CqY9n9O+XMgsJlUGpvuixIzPtxV0NTTKKr09He78mc0UCTiO+fCHFL/ecGc/PD13Z1QQ0769Nq/kakshAUu9Hr95X8B/D5eXmhLfbIQZ/936+vAFY6cIg5iM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495078; c=relaxed/simple; bh=RXv/8HHQlvGJZSc4bfEumgCJIypGPgEUU9zuekqRKBA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UYSTeaDy7wzLk2LkPiWIvca8F7sUs6m/lXmD03MfiSudsBnhPqs4nWb2q3S4DKalNo/BSOrAquOGSrSdTVPayVDv5JNKW9TRuaf2Cqd28fBrL6Ios76ymeng4dX/F22AmkyiXI01U+o4ydCmRAOfdt/uas+2zyJw96yIarpcjg8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=g3W9dzl7; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="g3W9dzl7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726495077; x=1758031077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RXv/8HHQlvGJZSc4bfEumgCJIypGPgEUU9zuekqRKBA=; b=g3W9dzl7hmbfKfThUfTyBrGkLuOkG+WM5PR6pPd+G8T/tKnDtJG9biVY du43TUzqb6IjPIBKA8n44wbNYv7v1+VogF5CY7cxv/qacRfZNX1Zvp1Kw ynCEeUEHPhPSPBjq/628Au/ja4I78OUWilUacQhjzTBboHyCnui51rAf5 +qhO5Bp/gfjtAYQ0AXvhujHZCHCAVmDSMPFPf8XXZ9DynBsgU3d+gugQE tYtbyQGjmMsQzA26QKfMV45IIy/NEbS/4ke25hi5uyAwxLdV/s7K4OvuG bPdLd+FSADieqKN689+940k2UfH0qYBKt842njDojzlLFWhZFDh8YOe/A A==; X-CSE-ConnectionGUID: VkFaXyq5SAmHGdhcrRfjSA== X-CSE-MsgGUID: w59++D3NQMS4Lf//ryjR6g== X-IronPort-AV: E=McAfee;i="6700,10204,11197"; a="36666849" X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="36666849" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:57:57 -0700 X-CSE-ConnectionGUID: 4zwEhaw6S1G1CnNDHHmD+g== X-CSE-MsgGUID: ybhIvE5zSYiERRB3DPu7ZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="68837371" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:57:52 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v6 06/12] spi: intel-dg: align 64bit read and write Date: Mon, 16 Sep 2024 16:49:22 +0300 Message-Id: <20240916134928.3654054-7-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916134928.3654054-1-alexander.usyskin@intel.com> References: <20240916134928.3654054-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 GSC SPI HW errors on quad access overlapping 1K border. Align 64bit read and write to avoid readq/writeq over 1K border. Signed-off-by: Alexander Usyskin --- drivers/spi/spi-intel-dg.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c index dfb457c43a5d..c76b0a70f8d8 100644 --- a/drivers/spi/spi-intel-dg.c +++ b/drivers/spi/spi-intel-dg.c @@ -231,6 +231,24 @@ static ssize_t spi_write(struct intel_dg_spi *spi, u8 region, len_s -= to_shift; } + if (!IS_ALIGNED(to, sizeof(u64)) && + ((to ^ (to + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data; + + memcpy(&data, &buf[0], sizeof(u32)); + spi_write32(spi, to, data); + if (spi_error(spi)) + return -EIO; + buf += sizeof(u32); + to += sizeof(u32); + len_s -= sizeof(u32); + } + len8 = ALIGN_DOWN(len_s, sizeof(u64)); for (i = 0; i < len8; i += sizeof(u64)) { u64 data; @@ -289,6 +307,23 @@ static ssize_t spi_read(struct intel_dg_spi *spi, u8 region, from += from_shift; } + if (!IS_ALIGNED(from, sizeof(u64)) && + ((from ^ (from + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data = spi_read32(spi, from); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[0], &data, sizeof(data)); + len_s -= sizeof(u32); + buf += sizeof(u32); + from += sizeof(u32); + } + len8 = ALIGN_DOWN(len_s, sizeof(u64)); for (i = 0; i < len8; i += sizeof(u64)) { u64 data = spi_read64(spi, from + i);