diff mbox series

[2/9] spi: spi_amd: Enable dual and quad I/O modes

Message ID 20240918105037.406003-3-Raju.Rangoju@amd.com (mailing list archive)
State Superseded
Headers show
Series spi: spi_amd: Performance Optimization Patch Series | expand

Commit Message

Raju Rangoju Sept. 18, 2024, 10:50 a.m. UTC 
The current spi_amd driver only supports single I/O mode, despite the AMD
SPI controller's capability for dual and quad I/O modes.  So, add support
to enable dual and quad I/O modes.

Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
 drivers/spi/spi-amd.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Mark Brown Sept. 19, 2024, 8:43 a.m. UTC | #1 
On Wed, Sep 18, 2024 at 04:20:30PM +0530, Raju Rangoju wrote:

>  {
>  	/* bus width is number of IO lines used to transmit */
> -	if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
> -	    op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA)
> +	if (op->cmd.buswidth > 1 || op->addr.buswidth > 4 ||
> +	    op->data.buswidth > 4 || op->data.nbytes > AMD_SPI_MAX_DATA)
>  		return false;

I'm not seeing anything where we tell the hardware about the width?
Raju Rangoju Sept. 24, 2024, 3:23 p.m. UTC | #2 
On 9/19/2024 2:13 PM, Mark Brown wrote:
> On Wed, Sep 18, 2024 at 04:20:30PM +0530, Raju Rangoju wrote:
> 
>>   {
>>   	/* bus width is number of IO lines used to transmit */
>> -	if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
>> -	    op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA)
>> +	if (op->cmd.buswidth > 1 || op->addr.buswidth > 4 ||
>> +	    op->data.buswidth > 4 || op->data.nbytes > AMD_SPI_MAX_DATA)
>>   		return false;
> 
> I'm not seeing anything where we tell the hardware about the width?

The hardware already supports single, dual, and quad I/O modes, and this 
functionality is enabled by default. No explicit software configuration 
is necessary to select the desired I/O mode. The hardware will 
automatically determine the appropriate mode based on the programmed 
opcode. This current patch is only intended to communicate these 
hardware capabilities to upper layers.
diff mbox series

Patch

diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c
index c52066360dfe..54b5a4d18691 100644
--- a/drivers/spi/spi-amd.c
+++ b/drivers/spi/spi-amd.c
@@ -364,8 +364,8 @@  static bool amd_spi_supports_op(struct spi_mem *mem,
 				const struct spi_mem_op *op)
 {
 	/* bus width is number of IO lines used to transmit */
-	if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
-	    op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA)
+	if (op->cmd.buswidth > 1 || op->addr.buswidth > 4 ||
+	    op->data.buswidth > 4 || op->data.nbytes > AMD_SPI_MAX_DATA)
 		return false;
 
 	return spi_mem_default_supports_op(mem, op);
@@ -514,7 +514,7 @@  static int amd_spi_probe(struct platform_device *pdev)
 	/* Initialize the spi_controller fields */
 	host->bus_num = 0;
 	host->num_chipselect = 4;
-	host->mode_bits = 0;
+	host->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD;
 	host->flags = SPI_CONTROLLER_HALF_DUPLEX;
 	host->max_speed_hz = AMD_SPI_MAX_HZ;
 	host->min_speed_hz = AMD_SPI_MIN_HZ;