From patchwork Mon Jul 27 08:59:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyrille Pitchen X-Patchwork-Id: 6869861 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7A9CAC05AD for ; Mon, 27 Jul 2015 08:59:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 506082069E for ; Mon, 27 Jul 2015 08:59:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AEF6A20660 for ; Mon, 27 Jul 2015 08:59:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752553AbbG0I7x (ORCPT ); Mon, 27 Jul 2015 04:59:53 -0400 Received: from eusmtp01.atmel.com ([212.144.249.243]:36731 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752296AbbG0I7w (ORCPT ); Mon, 27 Jul 2015 04:59:52 -0400 Received: from tenerife.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.31) with Microsoft SMTP Server id 14.3.235.1; Mon, 27 Jul 2015 10:59:50 +0200 From: Cyrille Pitchen To: , , , , , , , , , , CC: , , , , , , , , , Cyrille Pitchen Subject: [PATCH v3 1/5] mtd: spi-nor: notify (Q)SPI controller about protocol change Date: Mon, 27 Jul 2015 10:59:40 +0200 Message-ID: <36d261a6b16cb77a6faa0eb287164db15cc36acf.1437986785.git.cyrille.pitchen@atmel.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Once the Quad SPI mode has been enabled on a Micron flash memory, this device expects ALL the following commands to use the SPI 4-4-4 protocol. The (Q)SPI controller needs to be notified about the protocol change so it can adapt and keep on dialoging with the Micron memory. Signed-off-by: Cyrille Pitchen --- drivers/mtd/spi-nor/spi-nor.c | 21 +++++++++++++++++++++ include/linux/mtd/spi-nor.h | 13 +++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d78831b4422b..d373a5fdf48b 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -163,6 +163,22 @@ static inline int write_disable(struct spi_nor *nor) return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); } +/* + * Let the spi-nor framework notify lower layers, especially the driver of the + * (Q)SPI controller, about the new protocol to be used. Indeed, once the + * spi-nor framework has sent manufacturer specific commands to a memory to + * enable its Quad SPI mode, it should immediately after tell the QSPI + * controller to use the very same Quad SPI protocol as expected by the memory. + */ +static inline int spi_nor_set_protocol(struct spi_nor *nor, + enum spi_protocol proto) +{ + if (nor->set_protocol) + return nor->set_protocol(nor, proto); + + return 0; +} + static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return mtd->priv; @@ -943,6 +959,11 @@ static int micron_quad_enable(struct spi_nor *nor) return ret; } + /* switch protocol to Quad CMD 4-4-4 */ + ret = spi_nor_set_protocol(nor, SPI_PROTO_4_4_4); + if (ret) + return ret; + ret = spi_nor_wait_till_ready(nor); if (ret) return ret; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e5409524bb0a..1bf6f11310ef 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -87,6 +87,16 @@ enum read_mode { SPI_NOR_QUAD, }; +enum spi_protocol { + SPI_PROTO_1_1_1, /* SPI */ + SPI_PROTO_1_1_2, /* Dual Output */ + SPI_PROTO_1_1_4, /* Quad Output */ + SPI_PROTO_1_2_2, /* Dual IO */ + SPI_PROTO_1_4_4, /* Quad IO */ + SPI_PROTO_2_2_2, /* Dual Command */ + SPI_PROTO_4_4_4, /* Quad Command */ +}; + /** * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer * @wren: command for "Write Enable", or 0x00 for not required @@ -149,6 +159,7 @@ enum spi_nor_option_flags { * read/write/erase/lock/unlock operations * @read_xfer: [OPTIONAL] the read fundamental primitive * @write_xfer: [OPTIONAL] the writefundamental primitive + * @set_protocol: [OPTIONAL] notify about protocol change * @read_reg: [DRIVER-SPECIFIC] read out the register * @write_reg: [DRIVER-SPECIFIC] write data to the register * @read: [DRIVER-SPECIFIC] read data from the SPI NOR @@ -185,6 +196,8 @@ struct spi_nor { int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len, int write_enable); + int (*set_protocol)(struct spi_nor *nor, enum spi_protocol proto); + int (*read)(struct spi_nor *nor, loff_t from, size_t len, size_t *retlen, u_char *read_buf); void (*write)(struct spi_nor *nor, loff_t to,