From patchwork Fri Nov 28 03:45:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 5401221 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9CDA59F47A for ; Fri, 28 Nov 2014 03:45:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89C9A2013A for ; Fri, 28 Nov 2014 03:45:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 912C320138 for ; Fri, 28 Nov 2014 03:45:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750935AbaK1Dpr (ORCPT ); Thu, 27 Nov 2014 22:45:47 -0500 Received: from relmlor3.renesas.com ([210.160.252.173]:64401 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750784AbaK1Dpp (ORCPT ); Thu, 27 Nov 2014 22:45:45 -0500 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie2.idc.renesas.com with ESMTP; 28 Nov 2014 12:45:44 +0900 Received: from relmlac1.idc.renesas.com (relmlac1.idc.renesas.com [10.200.69.21]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 1190A4D673; Fri, 28 Nov 2014 12:45:44 +0900 (JST) Received: by relmlac1.idc.renesas.com (Postfix, from userid 0) id EE7558002E; Fri, 28 Nov 2014 12:45:43 +0900 (JST) Received: from relmlac1.idc.renesas.com (localhost [127.0.0.1]) by relmlac1.idc.renesas.com (Postfix) with ESMTP id E85E38002D; Fri, 28 Nov 2014 12:45:43 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac1.idc.renesas.com with ESMTP id NAE19280; Fri, 28 Nov 2014 12:45:43 +0900 X-IronPort-AV: E=Sophos;i="5.07,474,1413212400"; d="scan'208";a="174602431" Received: from mail-sg1lp0091.outbound.protection.outlook.com (HELO APAC01-SG1-obe.outbound.protection.outlook.com) ([207.46.51.91]) by relmlii1.idc.renesas.com with ESMTP/TLS/AES256-SHA; 28 Nov 2014 12:45:42 +0900 Received: from [10.161.20.147] (211.11.155.147) by HKNPR06MB321.apcprd06.prod.outlook.com (10.141.38.15) with Microsoft SMTP Server (TLS) id 15.1.26.15; Fri, 28 Nov 2014 03:45:39 +0000 Message-ID: <5477EFD7.50307@renesas.com> Date: Fri, 28 Nov 2014 12:45:27 +0900 From: Yoshihiro Shimoda User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: Mark Brown , "linux-spi@vger.kernel.org" , CC: , Laurent Pinchart , Rob Herring , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , "devicetree@vger.kernel.org" Subject: [PATCH][RFC] spi: sh-msiof: Configure MSIOF sync signal timing in device tree X-Originating-IP: [211.11.155.147] X-ClientProxiedBy: SIXPR06CA0037.apcprd06.prod.outlook.com (25.160.171.155) To HKNPR06MB321.apcprd06.prod.outlook.com (10.141.38.15) X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:HKNPR06MB321; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(7)(6); SRVR:HKNPR06MB321; X-Forefront-PRVS: 04097B7F7F X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(6049001)(6009001)(189002)(199003)(4396001)(87976001)(229853001)(107046002)(97736003)(64126003)(83506001)(106356001)(50986999)(95666004)(105586002)(65816999)(122386002)(54356999)(77096003)(77156002)(62966003)(99396003)(120916001)(42186005)(33656002)(101416001)(102836001)(31966008)(575784001)(19580405001)(23756003)(19580395003)(50466002)(65806001)(92726001)(40100003)(46102003)(92566001)(66066001)(86362001)(65956001)(36756003)(20776003)(21056001)(47776003); DIR:OUT; SFP:1102; SCL:1; SRVR:HKNPR06MB321; H:[10.161.20.147]; FPR:; SPF:None; MLV:sfv; PTR:InfoNoRecords; MX:1; A:1; LANG:en; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:HKNPR06MB321; X-OriginatorOrg: renesas.com Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The MSIOF controller has DTDL and SYNCDL in SITMDR1 and SIRMDR1 registers. So, this patch adds new properties like the following commit: d0fb47a5237d8b9576113568bacfd27892308b62 (spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT) The DTDL is the chip select (SYNC) setup time. b'000: No bit delay b'001: 1-clock-cycle delay b'010: 2-clock-cycle delay b'101: 0.5-clock-cycle delay b'110: 1.5-clock-cycle delay The SYNCDL is the chip select (SYNC) hold time. b'000: No bit delay b'001: 1-clock-cycle delay b'010: 2-clock-cycle delay b'011: 3-clock-cycle delay b'101: 0.5-clock-cycle delay b'110: 1.5-clock-cycle delay Signed-off-by: Yoshihiro Shimoda --- I would like to add new properties for sh-msiof driver to adjust the SYNC siginal timing using DTDL and SYNCDL. In the current driver, these parameters are hardcoded to 0. And then, I checked other spi drivers, and I found the following commit: d0fb47a5237d8b9576113568bacfd27892308b62 (spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT) If this patch is reasonable, I will modify the sh-msiof driver. Or, should we add a new function for this timing adjusting in the spi framework? Documentation/devicetree/bindings/spi/sh-msiof.txt | 8 ++++++++ drivers/spi/spi-sh-msiof.c | 2 ++ 2 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index d11c372..5fe8ffd 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -30,6 +30,14 @@ Optional properties: specifiers, one for transmission, and one for reception. - dma-names : Must contain a list of two DMA names, "tx" and "rx". +- renesas,tdmr-dtdl : delay sync signal (setup) in transmit mode + (default is 0, we can set it to 0, 1, 2, 5, or 6) +- renesas,tdmr-syncdl : delay sync signal (hold) in transmit mode + (default is 0, we can set it to 0, 1, 2, 3, 5, or 6) +- renesas,rdmr-dtdl : delay sync signal (setup) in receive mode + (default is 0, we can set it to 0, 1, 2, 5, or 6) +- renesas,rdmr-syncdl : delay sync signal (hold) in receive mode + (default is 0, we can set it to 0, 1, 2, 3, 5, or 6) Optional properties, deprecated for soctype-specific bindings: - renesas,tx-fifo-size : Overrides the default tx fifo size given in words diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 3f36540..09e0c38 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -296,11 +296,13 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; tmp |= !cs_high << MDR1_SYNCAC_SHIFT; tmp |= lsb_first << MDR1_BITLSB_SHIFT; +printk("%s: TMDR1 = %x\n", __func__, tmp | MDR1_TRMD | TMDR1_PCON); sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { /* These bits are reserved if RX needs TX */ tmp &= ~0x0000ffff; } +printk("%s: RMDR1 = %x\n", __func__, tmp); sh_msiof_write(p, RMDR1, tmp); tmp = 0;