diff mbox series

spi: fsl_spi: Don't change speed while chipselect is active

Message ID 8aab84c51aa330cf91f4b43782a1c483e150a4e3.1671025244.git.christophe.leroy@csgroup.eu (mailing list archive)
State Accepted
Commit 3b553e0041a65e499fa4e25ee146f01f4ec4e617
Headers show
Series spi: fsl_spi: Don't change speed while chipselect is active | expand

Commit Message

Christophe Leroy Dec. 14, 2022, 1:41 p.m. UTC
Commit c9bfcb315104 ("spi_mpc83xx: much improved driver") made
modifications to the driver to not perform speed changes while
chipselect is active. But those changes where lost with the
convertion to tranfer_one.

Previous implementation was allowing speed changes during
message transfer when cs_change flag was set.
At the time being, core SPI does not provide any feature to change
speed while chipselect is off, so do not allow any speed change during
message transfer, and perform the transfer setup in prepare_message
in order to set correct speed while chipselect is still off.

Reported-by: Herve Codina <herve.codina@bootlin.com>
Fixes: 64ca1a034f00 ("spi: fsl_spi: Convert to transfer_one")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Tested-by: Herve Codina <herve.codina@bootlin.com>
---
 drivers/spi/spi-fsl-spi.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

Comments

Herve Codina Dec. 14, 2022, 2:18 p.m. UTC | #1
Hi Christophe,

On Wed, 14 Dec 2022 14:41:33 +0100
Christophe Leroy <christophe.leroy@csgroup.eu> wrote:

> Commit c9bfcb315104 ("spi_mpc83xx: much improved driver") made
> modifications to the driver to not perform speed changes while
> chipselect is active. But those changes where lost with the
> convertion to tranfer_one.
> 
> Previous implementation was allowing speed changes during
> message transfer when cs_change flag was set.
> At the time being, core SPI does not provide any feature to change
> speed while chipselect is off, so do not allow any speed change during
> message transfer, and perform the transfer setup in prepare_message
> in order to set correct speed while chipselect is still off.
> 
> Reported-by: Herve Codina <herve.codina@bootlin.com>
> Fixes: 64ca1a034f00 ("spi: fsl_spi: Convert to transfer_one")
> Cc: stable@vger.kernel.org
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> Tested-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  drivers/spi/spi-fsl-spi.c | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
> index 731624f157fc..93152144fd2e 100644
> --- a/drivers/spi/spi-fsl-spi.c
> +++ b/drivers/spi/spi-fsl-spi.c
> @@ -333,13 +333,26 @@ static int fsl_spi_prepare_message(struct spi_controller *ctlr,
>  {
>  	struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
>  	struct spi_transfer *t;
> +	struct spi_transfer *first;
> +
> +	first = list_first_entry(&m->transfers, struct spi_transfer,
> +				 transfer_list);
>  
>  	/*
>  	 * In CPU mode, optimize large byte transfers to use larger
>  	 * bits_per_word values to reduce number of interrupts taken.
> +	 *
> +	 * Some glitches can appear on the SPI clock when the mode changes.
> +	 * Check that there is no speed change during the transfer and set it up
> +	 * now to change the mode without having a chip-select asserted.
>  	 */
> -	if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
> -		list_for_each_entry(t, &m->transfers, transfer_list) {
> +	list_for_each_entry(t, &m->transfers, transfer_list) {
> +		if (t->speed_hz != first->speed_hz) {
> +			dev_err(&m->spi->dev,
> +				"speed_hz cannot change during message.\n");
> +			return -EINVAL;
> +		}
> +		if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
>  			if (t->len < 256 || t->bits_per_word != 8)
>  				continue;
>  			if ((t->len & 3) == 0)
> @@ -348,7 +361,7 @@ static int fsl_spi_prepare_message(struct spi_controller *ctlr,
>  				t->bits_per_word = 16;
>  		}
>  	}
> -	return 0;
> +	return fsl_spi_setup_transfer(m->spi, first);
>  }
>  
>  static int fsl_spi_transfer_one(struct spi_controller *controller,

Looks good to me.

Reviewed-by: Herve Codina <herve.codina@bootlin.com>

Regards,
Hervé
Mark Brown Dec. 14, 2022, 6:40 p.m. UTC | #2
On Wed, 14 Dec 2022 14:41:33 +0100, Christophe Leroy wrote:
> Commit c9bfcb315104 ("spi_mpc83xx: much improved driver") made
> modifications to the driver to not perform speed changes while
> chipselect is active. But those changes where lost with the
> convertion to tranfer_one.
> 
> Previous implementation was allowing speed changes during
> message transfer when cs_change flag was set.
> At the time being, core SPI does not provide any feature to change
> speed while chipselect is off, so do not allow any speed change during
> message transfer, and perform the transfer setup in prepare_message
> in order to set correct speed while chipselect is still off.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: fsl_spi: Don't change speed while chipselect is active
      commit: 3b553e0041a65e499fa4e25ee146f01f4ec4e617

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark
diff mbox series

Patch

diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index 731624f157fc..93152144fd2e 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -333,13 +333,26 @@  static int fsl_spi_prepare_message(struct spi_controller *ctlr,
 {
 	struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
 	struct spi_transfer *t;
+	struct spi_transfer *first;
+
+	first = list_first_entry(&m->transfers, struct spi_transfer,
+				 transfer_list);
 
 	/*
 	 * In CPU mode, optimize large byte transfers to use larger
 	 * bits_per_word values to reduce number of interrupts taken.
+	 *
+	 * Some glitches can appear on the SPI clock when the mode changes.
+	 * Check that there is no speed change during the transfer and set it up
+	 * now to change the mode without having a chip-select asserted.
 	 */
-	if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
-		list_for_each_entry(t, &m->transfers, transfer_list) {
+	list_for_each_entry(t, &m->transfers, transfer_list) {
+		if (t->speed_hz != first->speed_hz) {
+			dev_err(&m->spi->dev,
+				"speed_hz cannot change during message.\n");
+			return -EINVAL;
+		}
+		if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 			if (t->len < 256 || t->bits_per_word != 8)
 				continue;
 			if ((t->len & 3) == 0)
@@ -348,7 +361,7 @@  static int fsl_spi_prepare_message(struct spi_controller *ctlr,
 				t->bits_per_word = 16;
 		}
 	}
-	return 0;
+	return fsl_spi_setup_transfer(m->spi, first);
 }
 
 static int fsl_spi_transfer_one(struct spi_controller *controller,