From patchwork Tue Dec 6 16:52:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyrille Pitchen X-Patchwork-Id: 9462905 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AE40260236 for ; Tue, 6 Dec 2016 16:54:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A068B28435 for ; Tue, 6 Dec 2016 16:54:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 953962847B; Tue, 6 Dec 2016 16:54:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CAB6228435 for ; Tue, 6 Dec 2016 16:53:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753052AbcLFQxy (ORCPT ); Tue, 6 Dec 2016 11:53:54 -0500 Received: from smtpout.microchip.com ([198.175.253.82]:41071 "EHLO email.microchip.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752780AbcLFQxx (ORCPT ); Tue, 6 Dec 2016 11:53:53 -0500 Received: from tenerife.corp.atmel.com (10.10.76.4) by chn-sv-exch05.mchp-main.com (10.10.76.106) with Microsoft SMTP Server id 14.3.181.6; Tue, 6 Dec 2016 09:53:47 -0700 From: Cyrille Pitchen To: CC: , , , , , , , Cyrille Pitchen Subject: [PATCH 2/2] mtd: spi-nor: add a stateless method to support memory size above 128Mib Date: Tue, 6 Dec 2016 17:52:32 +0100 Message-ID: <97e02fd9d6328bc591f98d5ae3da98b0ad9051d2.1481041702.git.cyrille.pitchen@atmel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAC+NgFtrCrMTGxcLF5cOiK/3WLcJg+u1LX9gtrs/bx2zRMWUVk8X9a6dZLDa0r2WyuPdpG6MDawBDFGtmXlJ+RQJrRtuRVpaCPq2Kh/NbWRsYLyp2MXJxCAmsY5TY+uwrexcjJwebgKHE2wdHWUFsEQFJiQ0nLjCCFDEL/GKUWDL7FzNIQlggVuLD93YWEJtFQEXi1tMjQHEODl6BeIlHc6tAwhICchI3z3WChTkFbCXWz2QDCQsJ2EisuPCPCcTmFRCUODnzCdgUZgEJiYMvXjBD1KhJLGxZwQwxJlCi4XE3K4TtJLFz+VQWCNtO4vD0i+wQtoPE0t9z2GFq2pe+garXltj+ah+UrSOx7WA/VK+txJ4ZE5kgbHeJB4+WQ9m+ErMeNkDVREm8nXeKZQKjxCwkp85CcuoCRqZVjNLOHn66wWG6rhHOHgamernJGQW6uYmZeXrJ+bmbGCHRlLWDsXeSv1QDY4gl59I8dfsp/59M/NL1oM4oXlqu/9DZKRPfu8+0jln/vOql08m3zz/vSlwvY86/fLpaYHRu0PnnhVePv50quL5Fdtn6X3Zh/885pMszCyZuzH4oy7WpKezuh+cZSRn+epxs2m7cp1T4Uk5ta5Nx+jtLeeU+Gf/79SHTeydpaXX5sPUUO7A9UmIpzkg01GIuKk4EADyTSAZHAgAA Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch provides an alternative mean to support memory above 16MiB (128Mib) by replacing 3byte address op codes by their associated 4byte address versions. Using the dedicated 4byte address op codes doesn't change the internal state of the SPI NOR memory as opposed to using other means such as updating a Base Address Register (BAR) and sending command to enter/leave the 4byte mode. Hence when a CPU reset occurs, early bootloaders don't need to be aware of BAR value or 4byte mode being enabled: they can still access the first 16MiB of the SPI NOR memory using the regular 3byte address op codes. Signed-off-by: Cyrille Pitchen Tested-by: Vignesh R --- drivers/mtd/spi-nor/spi-nor.c | 114 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 93 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8abe134e174a..606c030c566d 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -75,6 +75,10 @@ struct flash_info { * bit. Must be used with * SPI_NOR_HAS_LOCK. */ +#define SPI_NOR_4B_OPCODES BIT(10) /* + * Use dedicated 4byte address op codes + * to support memory size above 128Mib. + */ }; #define JEDEC_MFR(info) ((info)->id[0]) @@ -188,6 +192,91 @@ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) return mtd->priv; } + +struct spi_nor_address_entry { + u8 src_opcode; + u8 dst_opcode; +}; + +static u8 spi_nor_convert_opcode(u8 opcode, + const struct spi_nor_address_entry *entries, + size_t num_entries) +{ + int min, max; + + /* + * This function implements a dichotomic search in the entries[] + * array indexed by src_opcode. Hence we assume that the entries[] + * array is sorted by src_opcode. + * The dichotomic search has a logarithmic complexity as opposed + * to a simple loop on all entires, which has a linear complexity: + * it means that when n is the number of entries in the input array, + * the dichotomic search performs O(log2(n)) comparisons whereas + * a simple loop performs O(n) comparisons. + */ + min = 0; + max = num_entries - 1; + while (min <= max) { + int mid = (min + max) >> 1; + const struct spi_nor_address_entry *entry = &entries[mid]; + + if (opcode == entry->src_opcode) + return entry->dst_opcode; + + if (opcode < entry->src_opcode) + max = mid - 1; + else + min = mid + 1; + } + + /* No conversion found */ + return opcode; +} + +static u8 spi_nor_3to4_opcode(u8 opcode) +{ + /* MUST be sorted by 3byte opcode (cf spi_nor_convert_opcode). */ +#define ENTRY_3TO4(_opcode) { _opcode, _opcode##_4B } + static const struct spi_nor_address_entry spi_nor_3to4_table[] = { + ENTRY_3TO4(SPINOR_OP_PP), /* 0x02 */ + ENTRY_3TO4(SPINOR_OP_READ), /* 0x03 */ + ENTRY_3TO4(SPINOR_OP_READ_FAST), /* 0x0b */ + ENTRY_3TO4(SPINOR_OP_BE_4K), /* 0x20 */ + ENTRY_3TO4(SPINOR_OP_PP_1_1_4), /* 0x32 */ + ENTRY_3TO4(SPINOR_OP_PP_1_4_4), /* 0x38 */ + ENTRY_3TO4(SPINOR_OP_READ_1_1_2), /* 0x3b */ + ENTRY_3TO4(SPINOR_OP_BE_32K), /* 0x52 */ + ENTRY_3TO4(SPINOR_OP_READ_1_1_4), /* 0x6b */ + ENTRY_3TO4(SPINOR_OP_READ_1_2_2), /* 0xbb */ + ENTRY_3TO4(SPINOR_OP_SE), /* 0xd8 */ + ENTRY_3TO4(SPINOR_OP_READ_1_4_4), /* 0xeb */ + }; +#undef ENTRY_3TO4 + + return spi_nor_convert_opcode(opcode, spi_nor_3to4_table, + ARRAY_SIZE(spi_nor_3to4_table)); +} + +static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, + const struct flash_info *info) +{ + /* Do some manufacturer fixups first */ + switch (JEDEC_MFR(info)) { + case SNOR_MFR_SPANSION: + /* No small sector erase for 4-byte command set */ + nor->erase_opcode = SPINOR_OP_SE; + nor->mtd.erasesize = info->sector_size; + break; + + default: + break; + } + + nor->read_opcode = spi_nor_3to4_opcode(nor->read_opcode); + nor->program_opcode = spi_nor_3to4_opcode(nor->program_opcode); + nor->erase_opcode = spi_nor_3to4_opcode(nor->erase_opcode); +} + /* Enable/disable 4-byte addressing mode. */ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, int enable) @@ -1486,27 +1575,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) else if (mtd->size > 0x1000000) { /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; - if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { - /* Dedicated 4-byte command set */ - switch (nor->flash_read) { - case SPI_NOR_QUAD: - nor->read_opcode = SPINOR_OP_READ_1_1_4_4B; - break; - case SPI_NOR_DUAL: - nor->read_opcode = SPINOR_OP_READ_1_1_2_4B; - break; - case SPI_NOR_FAST: - nor->read_opcode = SPINOR_OP_READ_FAST_4B; - break; - case SPI_NOR_NORMAL: - nor->read_opcode = SPINOR_OP_READ_4B; - break; - } - nor->program_opcode = SPINOR_OP_PP_4B; - /* No small sector erase for 4-byte command set */ - nor->erase_opcode = SPINOR_OP_SE_4B; - mtd->erasesize = info->sector_size; - } else + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || + info->flags & SPI_NOR_4B_OPCODES) + spi_nor_set_4byte_opcodes(nor, info); + else set_4byte(nor, info, 1); } else { nor->addr_width = 3;