| Message ID | 987430ee905fd299fe962663d94f848b341c87df.1691047461.git.michal.simek@amd.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 88362275240303455bbec05c249daa84aff07059 |
| Headers | show |
| Series | [1/2] dt-bindings: spi: spi-cadence: Describe power-domains property | expand |
On Thu, Aug 03, 2023 at 09:24:24AM +0200, Michal Simek wrote: > ZynqMP Cadence SPI IP core has own power domain that's why describe it as > optional property. > > Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
On Thu, 03 Aug 2023 09:24:24 +0200, Michal Simek wrote: > ZynqMP Cadence SPI IP core has own power domain that's why describe it as > optional property. > > Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/2] dt-bindings: spi: spi-cadence: Describe power-domains property commit: 88362275240303455bbec05c249daa84aff07059 [2/2] dt-bindings: spi: spi-cadence: Add label property commit: ffae65fb1ae4738151158b4435fad822cb1ca29c All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml index b7552739b554..9eda7f0d2869 100644 --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml @@ -49,6 +49,9 @@ properties: enum: [ 0, 1 ] default: 0 + power-domains: + maxItems: 1 + required: - compatible - reg
ZynqMP Cadence SPI IP core has own power domain that's why describe it as optional property. Signed-off-by: Michal Simek <michal.simek@amd.com> --- Documentation/devicetree/bindings/spi/spi-cadence.yaml | 3 +++ 1 file changed, 3 insertions(+)