From patchwork Thu Apr 26 09:10:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10365075 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 579E5602DC for ; Thu, 26 Apr 2018 09:11:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3BFBB290BE for ; Thu, 26 Apr 2018 09:11:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 384D0290CD; Thu, 26 Apr 2018 09:11:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4414B29101 for ; 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Thu, 26 Apr 2018 04:10:01 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 26 Apr 2018 04:10:00 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 26 Apr 2018 04:10:01 -0500 Received: from [172.24.190.89] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3Q99tLe016934; Thu, 26 Apr 2018 04:09:56 -0500 Subject: Re: [PATCH v3 7/9] spi: ti-qspi: Implement the spi_mem interface To: Boris Brezillon , David Woodhouse , Brian Norris , Marek Vasut , Richard Weinberger , Cyrille Pitchen , , Miquel Raynal , Mark Brown , CC: Peter Pan , Frieder Schrempf , Yogesh Gaur , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Kamal Dasu , Maxime Chevallier References: <20180422183522.11118-1-boris.brezillon@bootlin.com> <20180422183522.11118-8-boris.brezillon@bootlin.com> From: Vignesh R Message-ID: Date: Thu, 26 Apr 2018 14:40:41 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180422183522.11118-8-boris.brezillon@bootlin.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Monday 23 April 2018 12:05 AM, Boris Brezillon wrote: > The spi_mem interface is meant to replace the spi_flash_read() one. > Implement the ->exec_op() method so that we can smoothly get rid of the > old interface. > > Signed-off-by: Boris Brezillon > --- > Changes in v3: > - none > > Changes in v2: > - include spi-mem.h > - treat op->addr.val differently since it's now an u64 > - Fix 'buf is DMA-able' check > - Extract max mmap size from resource_size() > --- > drivers/spi/spi-ti-qspi.c | 84 +++++++++++++++++++++++++++++++++++++++-------- > 1 file changed, 71 insertions(+), 13 deletions(-) > > diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c > index c24d9b45a27c..a37db01447a7 100644 > --- a/drivers/spi/spi-ti-qspi.c > +++ b/drivers/spi/spi-ti-qspi.c > @@ -36,6 +36,7 @@ > #include > > #include > +#include > > struct ti_qspi_regs { > u32 clkctrl; > @@ -50,6 +51,7 @@ struct ti_qspi { > struct spi_master *master; > void __iomem *base; > void __iomem *mmap_base; > + size_t mmap_size; > struct regmap *ctrl_base; > unsigned int ctrl_reg; > struct clk *fclk; > @@ -434,12 +436,10 @@ static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, > return 0; > } > > -static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, > - struct spi_flash_read_message *msg) > +static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs, > + void *to, size_t readsize) > { > - size_t readsize = msg->len; > - void *to = msg->buf; > - dma_addr_t dma_src = qspi->mmap_phys_base + msg->from; > + dma_addr_t dma_src = qspi->mmap_phys_base + offs; > int ret = 0; > > /* > @@ -507,13 +507,14 @@ static void ti_qspi_disable_memory_map(struct spi_device *spi) > qspi->mmap_enabled = false; > } > > -static void ti_qspi_setup_mmap_read(struct spi_device *spi, > - struct spi_flash_read_message *msg) > +static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode, > + u8 data_nbits, u8 addr_width, > + u8 dummy_bytes) > { > struct ti_qspi *qspi = spi_master_get_devdata(spi->master); > - u32 memval = msg->read_opcode; > + u32 memval = opcode; > > - switch (msg->data_nbits) { > + switch (data_nbits) { > case SPI_NBITS_QUAD: > memval |= QSPI_SETUP_RD_QUAD; > break; > @@ -524,8 +525,8 @@ static void ti_qspi_setup_mmap_read(struct spi_device *spi, > memval |= QSPI_SETUP_RD_NORMAL; > break; > } > - memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT | > - msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT); > + memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT | > + dummy_bytes << QSPI_SETUP_DUMMY_SHIFT); > ti_qspi_write(qspi, memval, > QSPI_SPI_SETUP_REG(spi->chip_select)); > } > @@ -546,13 +547,15 @@ static int ti_qspi_spi_flash_read(struct spi_device *spi, > > if (!qspi->mmap_enabled) > ti_qspi_enable_memory_map(spi); > - ti_qspi_setup_mmap_read(spi, msg); > + ti_qspi_setup_mmap_read(spi, msg->read_opcode, msg->data_nbits, > + msg->addr_width, msg->dummy_bytes); > > if (qspi->rx_chan) { > if (msg->cur_msg_mapped) > ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from); > else > - ret = ti_qspi_dma_bounce_buffer(qspi, msg); > + ret = ti_qspi_dma_bounce_buffer(qspi, msg->from, > + msg->buf, msg->len); > if (ret) > goto err_unlock; > } else { > @@ -566,6 +569,58 @@ static int ti_qspi_spi_flash_read(struct spi_device *spi, > return ret; > } > > +static int ti_qspi_exec_mem_op(struct spi_mem *mem, > + const struct spi_mem_op *op) > +{ > + struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master); > + u32 from = 0; > + int ret = 0; > + > + /* Only optimize read path. */ > + if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN || > + !op->addr.nbytes || op->addr.nbytes > 4) > + return -ENOTSUPP; > + > + /* Address exceeds MMIO window size, fall back to regular mode. */ > + from = op->addr.val; > + if (from + op->data.nbytes > qspi->mmap_size) > + return -ENOTSUPP; > + qspi->mmap_size turns out to be 0 if qspi->rx_chan is not NULL (in other words when DMA is used) Could you squash below diff into this patch? > + mutex_lock(&qspi->list_lock); > + > + if (!qspi->mmap_enabled) > + ti_qspi_enable_memory_map(mem->spi); > + ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth, > + op->addr.nbytes, op->dummy.nbytes); > + > + if (qspi->rx_chan) { > + struct sg_table sgt; > + > + if (virt_addr_valid(op->data.buf.in) && > + !spi_controller_dma_map_mem_op_data(mem->spi->master, op, > + &sgt)) { > + ret = ti_qspi_dma_xfer_sg(qspi, sgt, from); > + spi_controller_dma_unmap_mem_op_data(mem->spi->master, > + op, &sgt); > + } else { > + ret = ti_qspi_dma_bounce_buffer(qspi, from, > + op->data.buf.in, > + op->data.nbytes); > + } > + } else { > + memcpy_fromio(op->data.buf.in, qspi->mmap_base + from, > + op->data.nbytes); > + } > + > + mutex_unlock(&qspi->list_lock); > + > + return ret; > +} > + > +static const struct spi_controller_mem_ops ti_qspi_mem_ops = { > + .exec_op = ti_qspi_exec_mem_op, > +}; > + > static int ti_qspi_start_transfer_one(struct spi_master *master, > struct spi_message *m) > { > @@ -673,6 +728,7 @@ static int ti_qspi_probe(struct platform_device *pdev) > master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | > SPI_BPW_MASK(8); > master->spi_flash_read = ti_qspi_spi_flash_read; > + master->mem_ops = &ti_qspi_mem_ops; > > if (!of_property_read_u32(np, "num-cs", &num_cs)) > master->num_chipselect = num_cs; > @@ -778,6 +834,7 @@ static int ti_qspi_probe(struct platform_device *pdev) > > no_dma: > if (!qspi->rx_chan && res_mmap) { > + qspi->mmap_size = resource_size(res_mmap); > qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); > if (IS_ERR(qspi->mmap_base)) { > dev_info(&pdev->dev, > @@ -785,6 +842,7 @@ static int ti_qspi_probe(struct platform_device *pdev) > PTR_ERR(qspi->mmap_base)); > qspi->mmap_base = NULL; > master->spi_flash_read = NULL; > + master->mem_ops = NULL; > } > } > qspi->mmap_enabled = false; > =========== diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 694902dd6f70..c54b760e00ed 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -718,6 +718,7 @@ static int ti_qspi_probe(struct platform_device *pdev) "memory mapped resource not required\n"); } } + qspi->mmap_size = resource_size(res_mmap); irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -794,7 +795,6 @@ static int ti_qspi_probe(struct platform_device *pdev) no_dma: if (!qspi->rx_chan && res_mmap) { - qspi->mmap_size = resource_size(res_mmap); qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); if (IS_ERR(qspi->mmap_base)) { dev_info(&pdev->dev,