From patchwork Fri Sep 8 08:33:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolin Wang X-Patchwork-Id: 9943407 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8A461604D4 for ; Fri, 8 Sep 2017 08:36:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 744782855A for ; Fri, 8 Sep 2017 08:36:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 662A52858A; Fri, 8 Sep 2017 08:36:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B342C2855A for ; Fri, 8 Sep 2017 08:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754792AbdIHIgp (ORCPT ); Fri, 8 Sep 2017 04:36:45 -0400 Received: from sci-ig2.spreadtrum.com ([222.66.158.135]:25741 "EHLO SHSQR01.spreadtrum.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1751718AbdIHIgo (ORCPT ); Fri, 8 Sep 2017 04:36:44 -0400 Received: from ig2.spreadtrum.com (shmbx04.spreadtrum.com [10.0.1.214]) by SHSQR01.spreadtrum.com with ESMTP id v888Xi3x005417 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 8 Sep 2017 16:33:44 +0800 (CST) (envelope-from Orson.Zhai@spreadtrum.com) Received: from SHCAS02.spreadtrum.com (10.0.1.202) by SHMBX04.spreadtrum.com (10.0.1.214) with Microsoft SMTP Server (TLS) id 15.0.847.32; Fri, 8 Sep 2017 16:33:49 +0800 Received: from localhost (10.0.73.143) by SHCAS02.spreadtrum.com (10.0.1.250) with Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend Transport; Fri, 8 Sep 2017 16:33:49 +0800 From: Baolin Wang To: , , CC: , , , , Subject: [PATCH v2 1/2] dt-bindings: spi: Add Spreadtrum ADI controller documentation Date: Fri, 8 Sep 2017 16:33:41 +0800 Message-ID: X-Mailer: git-send-email 2.12.2 MIME-Version: 1.0 X-MAIL: SHSQR01.spreadtrum.com v888Xi3x005417 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the binding documentation for Spreadtrum ADI controller device. Signed-off-by: Baolin Wang --- Changes since v1: - Add more documentation the 'sprd,hw-channels' property and why need one hardware spinlock. --- .../devicetree/bindings/spi/spi-sprd-adi.txt | 58 ++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-sprd-adi.txt diff --git a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt new file mode 100644 index 0000000..0f76336 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt @@ -0,0 +1,58 @@ +Spreadtrum ADI controller based on SPI framework + +ADI is the abbreviation of Anolog-Digital interface, which is used to access +analog chip (such as PMIC) from digital chip. ADI controller follows the SPI +framework for its hardware implementation is alike to SPI bus and its timing +is compatile to SPI timing. + +ADI controller has 50 channels including 2 software read/write channels and +48 hardware channels to access analog chip. For 2 software read/write channels, +users should set ADI registers to access analog chip. For hardware channels, +we can configure them to allow other hardware components to use it independently, +which means we can just link one analog chip address to one hardware channel, +then users can access the mapped analog chip address by this hardware channel +triggered by hardware components instead of ADI software channels. + +Thus we introduce one property named "sprd,hw-channels" to configure hardware +channels, the first value specifies the hardware channel id which is used to +transfer data triggered by hardware automatically, and the second value specifies +the analog chip address where user want to access by hardware components. + +Another hand since we have multi-subsystems will use unique ADI to access analog +chip, when one system is reading/writing data by ADI software channels, that +should be under one hardware spinlock protection to prevent other systems from +reading/writing data by ADI software channels at the same time, or two parallel +routine of setting ADI registers will make ADI controller registers chaos to +lead incorrect results. Then we need one hardware spinlock to synchronize between +the multiple subsystems. + +Required properties: +- compatible: Should be "sprd,sc9860-adi". +- reg: Offset and length of ADI-SPI controller register space. +- hwlocks: Reference to a phandle of a hwlock provider node. +- hwlock-names: Reference to hwlock name strings defined in the same order + as the hwlocks, should be "adi". +- #address-cells: Number of cells required to define a chip select address + on the ADI-SPI bus. Should be set to 1. +- #size-cells: Size of cells required to define a chip select address size + on the ADI-SPI bus. Should be set to 0. + +Optional properties: +- sprd,hw-channels: The first value specifies the hardware channel id which + is used to transfer data triggered by hardware automatically, and + the second value specifies the analog chip address where user want + to access by hardware components. + +SPI slave nodes must be children of the SPI controller node and can contain +properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. + +Example: + adi_bus: spi@40030000 { + compatible = "sprd,sc9860-adi"; + reg = <0 0x40030000 0 0x10000>; + hwlocks = <&hwlock1 0>; + hwlock-names = "adi"; + #address-cells = <1>; + #size-cells = <0>; + sprd,hw-channels = <30 0x8c20>; + };