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Tue, 14 Feb 2023 03:56:01 -0800 From: Dipen Patel To: , , , , , , , , , CC: Dipen Patel Subject: [PATCH V2 4/6] dt-bindings: timestamp: Add Tegra234 support Date: Tue, 14 Feb 2023 03:55:51 -0800 Message-ID: <20230214115553.10416-5-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214115553.10416-1-dipenp@nvidia.com> References: <20230214115553.10416-1-dipenp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: timestamp@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT060:EE_|CH3PR12MB8725:EE_ X-MS-Office365-Filtering-Correlation-Id: af894e40-d107-416d-e17c-08db0e82768e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lHtMIocQ+WwV7i3aTPtXyyWdyylf2g7i8b6KTJHLy+eVd7uDamZGrUyalNY3tnn74JxN4it1Wwq1l3qIrR6Ia5dI7OybSj5fXpcmwIMFJlrvltwp/DmE5yYPJzOK/qVb3HKBwF6RgdcyfYM5r//+wSkoFguzqKYgndQSlGeGPCsc4pXcu+lrdDF3QSnKkEqbNWQOSjbkS/rmcLDqN0mb0fqUayyPHhw+1BZntA+42Pi/zyQBJSONgMBf9bPLk8MFLUQOFozhqfvrreYeRhRSJnad6n1VKkfsnB0oPZ2rCKZNIgcloHQYUIwrp/wDdNzSYZk1AaLATmkHAtwYdUtFRzV5llROE7A+YM2SvxxyqZiuwdkFSpYpeijYhQGjPT7ZrNeAmIYZI9vr1BqwaB8RQ0yhHZ0gKeRn4a5qhbiXz5Mgxd2uyhJrXtyXhLUUkn0HVXMeu5HCJmrlBrkZFUBfggRRAGex2JGISOswhWqL4H/eZSBKw9k+udiYOD82EDG5rG4ua/uq7eHwYFu4pgObMAk9ebn4FU+mQy9gaOVB5ojEPtiITmiSg4fLGCyfuRLcSrE3t98b0ZVQz2VV3eoXy7zSeKYrU5GyT99WT5gg17NUEQpxI91gmMG4wwGyDbbp4kDQy1rmu5QHDtYy4dFn53ZgaHk9wwS3uCodzUhyqKfh8USr7yMEeTCUmLq0Dyk5oz/sxC48Mo3r57/zKNpsXSSj3zMp3bXBqUmM6swwyYNHfkVXQQSPHiDrbmnlewwVe/6PngArqvEMfpkG+RYQcBOMPx0YOh9ZF2wR7oRGmZESvcgL7/yT9iLa89EWXkxM5tpePckakf+to8ftR4N2hg6CAgBdzRKpGMBkxs0cySk= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199018)(36840700001)(46966006)(40470700004)(5660300002)(47076005)(83380400001)(26005)(186003)(426003)(2906002)(36756003)(110136005)(82310400005)(40460700003)(1076003)(86362001)(107886003)(478600001)(41300700001)(6666004)(7696005)(966005)(7636003)(82740400003)(36860700001)(40480700001)(356005)(2616005)(336012)(8676002)(8936002)(921005)(316002)(70206006)(4326008)(70586007)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 11:56:09.9107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af894e40-d107-416d-e17c-08db0e82768e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8725 Added timestamp provider support for the Tegra234 in devicetree bindings. Signed-off-by: Dipen Patel --- v2: - Removed nvidia,slices property - Added nvidia,gpio-controller based on review comments from Thierry, this will help simplify the hte provider driver. .../timestamp/nvidia,tegra194-hte.yaml | 30 ++++++++++++------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index c31e207d1652..d0f4ed75baee 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra194 on chip generic hardware timestamping engine (HTE) +title: Tegra on chip generic hardware timestamping engine (HTE) provider maintainers: - Dipen Patel @@ -23,6 +23,8 @@ properties: enum: - nvidia,tegra194-gte-aon - nvidia,tegra194-gte-lic + - nvidia,tegra234-gte-aon + - nvidia,tegra234-gte-lic reg: maxItems: 1 @@ -38,14 +40,11 @@ properties: minimum: 1 maximum: 256 - nvidia,slices: - $ref: /schemas/types.yaml#/definitions/uint32 + nvidia,gpio-controller: + $ref: /schemas/types.yaml#/definitions/phandle description: - HTE lines are arranged in 32 bit slice where each bit represents different - line/signal that it can enable/configure for the timestamp. It is u32 - property and depends on the HTE instance in the chip. The value 3 is for - GPIO GTE and 11 for IRQ GTE. - enum: [3, 11] + The phandle to AON gpio controller instance. This is required to handle + namespace conversion between GPIO and GTE. '#timestamp-cells': description: @@ -55,11 +54,21 @@ properties: mentioned in the nvidia GPIO device tree binding document. const: 1 +if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-aon + - nvidia,tegra234-gte-aon +then: + required: + - nvidia,gpio-controller + required: - compatible - reg - interrupts - - nvidia,slices - "#timestamp-cells" additionalProperties: false @@ -71,7 +80,7 @@ examples: reg = <0xc1e0000 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <3>; + nvidia,gpio-controller = <&gpio_aon>; #timestamp-cells = <1>; }; @@ -81,7 +90,6 @@ examples: reg = <0x3aa0000 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <11>; #timestamp-cells = <1>; };