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Thu, 13 Apr 2023 17:45:01 -0700 From: Dipen Patel To: , , , , , , , , , , , , , CC: Dipen Patel Subject: [V6 7/9] hte: Deprecate nvidia,slices property Date: Thu, 13 Apr 2023 17:44:53 -0700 Message-ID: <20230414004455.19275-8-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230414004455.19275-1-dipenp@nvidia.com> References: <20230414004455.19275-1-dipenp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: timestamp@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT074:EE_|MN2PR12MB4223:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c8196aa-52cc-4230-7070-08db3c817ef5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZTgySec1L2xqggaFlmiCp7Ce3Nhs0Zc9fhShYUD88qhfAmvzv2ZdyFc66eUYEa/4dWm7XqijHx84oL2metwn++gma5StrhZkNTZjJlPw4s+dTHQDB8uZsDDIhyqMKntqBpTEhEJu3/pdg1cuipn2WFT8e9hN52BGG5G4yIKW9gWZIMIiP35PeS4rT6jEPrTdzCaLIlhp5A94bBO7K3ArfY5cqRM6ux3EXZzqYPu+fmZuuPCiPTL+UsYBNGHGi7iU0AsfqzKKJKT7yZtWu+gCtz21L9PTPV25b+W2/kQV6M90Tlxg4rZ0tYbSp4VU/DMwKwSERW633WmGlggY1wlscwpxkSM/PCgieR7h6knhogeHxOWZIvUSJRAnAmJn0M+neOgp0bAx7Hk94sjfQ9pPZr8tkpSgALrneacQx1KyfmuKMeiYstNoMAD/fF7klWQohw32zliEYERcZJrb0vqE/et721pv9jfqW18DIo1WEv5usCY2Kr2rAjI2JtTJbb0Dz4lc39OmAYxhP1XuxdwDxWE/KmD+vnWMriffW72aDb1A8F/7RBpyTEn2Cj7nkFk8lmUK0bs/Q/bacnfH6WvDZ6rwAZ0ArOdX+YOFpXc+oyI5Xf4r0irA/5hJrLcbTeXX1ZrkXX+LWCYpM6MdbojUvyukpfkKLXHmSF9+Xt4XkCraYWdjm3QxKN37t2+TneTqXBX42JT+vPwzwnMRuIDVWsP6keYjfeDR3ttQyl72kcJAwwl3NigBtDZczrlnFey6tXurBx72HPWl4/Tay0qx7cEz5YYO4cGKmcF1FA8ls//0uLZqyNlM1p8AkA/rqdBh9aAV/j1uqMj6+biPvoS6sJp9UrwiByDxLodKCC2XDR8vBvv90d5eJVmuzc3rPSLW X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(376002)(396003)(346002)(5400799015)(451199021)(36840700001)(46966006)(40470700004)(86362001)(110136005)(7416002)(34020700004)(40460700003)(921005)(316002)(7636003)(356005)(478600001)(41300700001)(82740400003)(8676002)(8936002)(5660300002)(70206006)(40480700001)(70586007)(107886003)(36756003)(426003)(336012)(1076003)(26005)(186003)(36860700001)(4326008)(6666004)(83380400001)(2906002)(7696005)(2616005)(82310400005)(47076005)(83996005)(2101003)(12100799027);DIR:OUT;SFP:1501; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 00:45:08.0581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c8196aa-52cc-4230-7070-08db3c817ef5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4223 The relevant DT bindings deprecates nvidia,slices property from Tegra234 SoC onwards, moving the slices value per SoC data structure instead. Signed-off-by: Dipen Patel --- drivers/hte/hte-tegra194.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 5d1f947db0f6..945c68c5e476 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -118,6 +118,7 @@ struct tegra_hte_line_data { struct tegra_hte_data { enum tegra_hte_type type; + u32 slices; u32 map_sz; u32 sec_map_sz; const struct tegra_hte_line_mapped *map; @@ -323,6 +324,7 @@ static const struct tegra_hte_data t194_aon_hte = { .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), .sec_map = tegra194_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; static const struct tegra_hte_data t234_aon_hte = { @@ -331,12 +333,21 @@ static const struct tegra_hte_data t234_aon_hte = { .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), .sec_map = tegra234_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; -static const struct tegra_hte_data lic_hte = { +static const struct tegra_hte_data t194_lic_hte = { .map_sz = 0, .map = NULL, .type = HTE_TEGRA_TYPE_LIC, + .slices = 11, +}; + +static const struct tegra_hte_data t234_lic_hte = { + .map_sz = 0, + .map = NULL, + .type = HTE_TEGRA_TYPE_LIC, + .slices = 17, }; static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) @@ -639,9 +650,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, } static const struct of_device_id tegra_hte_of_match[] = { - { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, - { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; @@ -679,13 +690,6 @@ static int tegra_hte_probe(struct platform_device *pdev) dev = &pdev->dev; - ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); - if (ret != 0) { - dev_err(dev, "Could not read slices\n"); - return -EINVAL; - } - nlines = slices << 5; - hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); if (!hte_dev) return -ENOMEM; @@ -697,6 +701,13 @@ static int tegra_hte_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, hte_dev); hte_dev->prov_data = of_device_get_match_data(&pdev->dev); + ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); + if (ret != 0) + slices = hte_dev->prov_data->slices; + + dev_dbg(dev, "slices:%d\n", slices); + nlines = slices << 5; + hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hte_dev->regs)) return PTR_ERR(hte_dev->regs);