| Message ID | 20220520133746.66142-1-roger.pau@citrix.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | x86/lbr: handle lack of model-specific LBRs | expand |
Hi, It seems that this series [1] has been stale for a while, with actions needed from the author for the first 4 patches and comments needed from the maintainers for the patch#5. So sending this email as a gentle reminder. Thanks! [1] https://patchwork.kernel.org/project/xen-devel/list/?series=643625 Kind regards, Henry > -----Original Message----- > From: Xen-devel <xen-devel-bounces@lists.xenproject.org> On Behalf Of > Roger Pau Monne > Subject: [PATCH 0/5] x86/lbr: handle lack of model-specific LBRs > > Hello, > > Intel Sapphire Rapids CPUs doesn't have model-specific MSRs, and hence > only architectural LBRs are available. > > Firstly implement some changes so Xen knows how to enable arch LBRs so > that the ler option can also work in such scenario (first two patches). > > The lack of model-specific LBRs also affects guests, as setting > DEBUGCTLMSR.LBR is now ignored (value hardwired to 0, writes ignored) > by > the hardware due to the lack of model-specific LBRs. The LBR format > reported in PERF_CAPABILITIES also need to be exposed, as that's a way > for guests to detect lack of model-specific LBRs presence (patches 3 > and 4). > > Patch 5 is an indentation fix that can be merged into patch 4: done > separately to help readability of patch 4. > > Thanks, Roger. > > Roger Pau Monne (5): > x86/ler: use feature flag to check if option is enabled > x86/lbr: enable hypervisor LER with arch LBR > x86/perf: expose LBR format in PERF_CAPABILITIES > x86/vmx: handle no model-specific LBR presence > x86/vmx: fix indentation of LBR > > xen/arch/x86/hvm/vmx/vmx.c | 59 ++++++++++++++------- > xen/arch/x86/include/asm/msr-index.h | 18 +++++++ > xen/arch/x86/msr.c | 9 ++++ > xen/arch/x86/traps.c | 29 ++++++++-- > xen/arch/x86/x86_64/traps.c | 2 +- > xen/include/public/arch-x86/cpufeatureset.h | 3 +- > 6 files changed, 97 insertions(+), 23 deletions(-) > > -- > 2.36.0 >
Hi, It seems that this series has been stale for more than a month, so I am sending this email as a gentle reminder with current status: Patch #2, #3 might need further actions from the maintainers Patch #4 might need further actions from the author. Patch #1 #5 has been reviewed/acked. Kind regards, Henry > -----Original Message----- > Subject: [PATCH 0/5] x86/lbr: handle lack of model-specific LBRs > > Hello, > > Intel Sapphire Rapids CPUs doesn't have model-specific MSRs, and hence > only architectural LBRs are available. > > Firstly implement some changes so Xen knows how to enable arch LBRs so > that the ler option can also work in such scenario (first two patches). > > The lack of model-specific LBRs also affects guests, as setting > DEBUGCTLMSR.LBR is now ignored (value hardwired to 0, writes ignored) by > the hardware due to the lack of model-specific LBRs. The LBR format > reported in PERF_CAPABILITIES also need to be exposed, as that's a way > for guests to detect lack of model-specific LBRs presence (patches 3 > and 4). > > Patch 5 is an indentation fix that can be merged into patch 4: done > separately to help readability of patch 4. > > Thanks, Roger. > > Roger Pau Monne (5): > x86/ler: use feature flag to check if option is enabled > x86/lbr: enable hypervisor LER with arch LBR > x86/perf: expose LBR format in PERF_CAPABILITIES > x86/vmx: handle no model-specific LBR presence > x86/vmx: fix indentation of LBR > > xen/arch/x86/hvm/vmx/vmx.c | 59 ++++++++++++++------- > xen/arch/x86/include/asm/msr-index.h | 18 +++++++ > xen/arch/x86/msr.c | 9 ++++ > xen/arch/x86/traps.c | 29 ++++++++-- > xen/arch/x86/x86_64/traps.c | 2 +- > xen/include/public/arch-x86/cpufeatureset.h | 3 +- > 6 files changed, 97 insertions(+), 23 deletions(-) > > -- > 2.36.0 >