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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Rahul Singh , Jan Beulich , "Paul Durrant" , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 0/8] SMMU handling for PCIe Passthrough on ARM Date: Thu, 11 May 2023 15:16:46 -0400 Message-ID: <20230511191654.400720-1-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT056:EE_|BN9PR12MB5322:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d6b2846-75eb-47c5-bebe-08db525455de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Zu7MhSvkpLg9Tat4Uy3N8cBzyW2XyyWDwM4J2KsVskuV698JvnOXTk8mESWh7FkXpdgt9i8jDSLYcwvPfevNDkAfgtizCAZyUMn28RGjq60CJhqjzkot9jSw1JBIiGtxJIpAz12RR6XdAb3rxK6xDcAslsazkmKGUFc76yrz2IPDApWZmvCcN+3MDJDAec7+fuDznMRAWMBNOqby0a2iInnx6KSr4VVCZlQix5XwHCuSztsYjBAZqY+y1bXlPSeliHaRYGmQMle1fuZ+Wh6MP3JYQxh6Ktt6wK5UNwNE4JYAxs3zIwJPKot2jsd2DPbeBGyBW8e8A02+PLH6Zd29LdGsL52x77fQzKKUAMUqehlq+QH0M/HqNdc6dVUa8IXvZrZAhLcz5NrnR9vmyFHpIi/wAG/RRoK3r6F7O+lDO4o+sW+tY2G1Zh827t5aaM4jroqmr6kBCSM1K3Ne8vlLi7kM9PRu6IzQRLkhgNQKZw5G+U7LVTGzsxQ8WSbrvSd7rMhqDp+du+jqRoxXLYJQ/GAAikBhg8w+hOuRBbZAz/Q+XIbwK5/CqUY6YrOoth0L9NpJewIWqoKZoudAwRx4j+H1hmZ796lY2iHeNc2KhKQa0CkXUSgROcyz6jJsCsMWYO/c0fFnYbtCh8+OI/69z1rgLu4bxghaOVBE1Qn5Iar0IXWKAQEs2p9ASxj88S4G2EoS5o37XZjDc8XWmAv1iqGt6CTjXVK6CtoTEXkAGGfIvI7UJAJUdHPmaWLW8KdZiPgiliWpMDzQ0WFUgY2/Jg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(396003)(136003)(39860400002)(376002)(451199021)(46966006)(36840700001)(40470700004)(336012)(426003)(2616005)(26005)(36860700001)(1076003)(41300700001)(47076005)(83380400001)(186003)(6666004)(478600001)(40460700003)(54906003)(4326008)(6916009)(82740400003)(70206006)(70586007)(40480700001)(356005)(316002)(81166007)(5660300002)(44832011)(86362001)(2906002)(36756003)(82310400005)(8936002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2023 19:17:17.3667 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d6b2846-75eb-47c5-bebe-08db525455de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5322 This series introduces SMMU handling for PCIe passthrough on ARM. These patches are independent from (and don't depend on) the vPCI reference counting/locking work in progress, and should be able to be upstreamed independently. v1-v2: * phantom device handling * shuffle around iommu_add_dt_pci_device() Oleksandr Andrushchenko (1): xen/arm: smmuv2: Add PCI devices support for SMMUv2 Oleksandr Tyshchenko (4): xen/arm: Move is_protected flag to struct device iommu/arm: Add iommu_dt_xlate() iommu/arm: Introduce iommu_add_dt_pci_device API pci/arm: Use iommu_add_dt_pci_device() Rahul Singh (1): xen/arm: smmuv3: Add PCI devices support for SMMUv3 Stewart Hildebrand (2): iommu/arm: iommu_add_dt_pci_device phantom handling RFC: pci/arm: don't do iommu call for phantom functions xen/arch/arm/domain_build.c | 4 +- xen/arch/arm/include/asm/device.h | 13 ++ xen/common/device_tree.c | 2 +- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 8 +- xen/drivers/passthrough/arm/smmu-v3.c | 74 +++++++- xen/drivers/passthrough/arm/smmu.c | 110 +++++++++--- xen/drivers/passthrough/device_tree.c | 218 ++++++++++++++++++++--- xen/drivers/passthrough/pci.c | 21 ++- xen/include/xen/device_tree.h | 38 ++-- xen/include/xen/iommu.h | 6 +- 10 files changed, 417 insertions(+), 77 deletions(-)