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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id 2-20020a05600c22c200b003f42328b5d9sm24857485wmg.39.2023.05.15.04.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 May 2023 04:31:40 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 10b400dc-f314-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1684150301; x=1686742301; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=GcS0sFy1j+iBirD4dRuPYJrHtHgaoJyuoMIW8QbN+lY=; b=EvSyOXYOhoECtJSlqGBVgwanO9Uxg8r9uzRPIB5gUBORfCsOUdF4bkq5T4R8FVj/PD v577vCRVd8RVg4/VR1WRb6l1jj9IW1/xG846OqHybl9AT+xntr/cygtKJqHSe79a2aqQ AtypoBa3MunRWY/VDbCVZ52zM7mMgvE8nHJCA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684150301; x=1686742301; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=GcS0sFy1j+iBirD4dRuPYJrHtHgaoJyuoMIW8QbN+lY=; b=hTnv1za3mCaIBqd8TWLWeeF5bcTaW2wVEzAqugvcaKzvX/8AjFL+9Q+9Bzbe3Krdtg G/IJG5NwakljxAkXOnKINALCeAGohALgeUsdk0Nm3GWASZp3/Q9NDwpY2qujOR5qKDqZ PyYXjU6m1qDwRIs2OkxgFO5gcYqVMVzBbs5pL2i5o7x96p2DwXxxb2XOim015aaDTT// 2LqHDm9snc4o8VuAufOeUEpAURNgyuwmbC1qA80lwTz4/L8vUVVtNswr8DuqCXjLLmWq o8aVwROuviOjQD5mUwH7Y2h5oF/P4tVwTiC8YReGIWno4OoaJJlLx5kVuv2PXVpwPE/D Gv3w== X-Gm-Message-State: AC+VfDxuW0FHqNRFU3NyynL3q0UZpQ7cahla/ynjs2wI92XDY7LN8cAm AY0PmgDE/bFuYEnbTIIldy9WTrbrVgpJJgweJYY= X-Google-Smtp-Source: ACHHUZ6RscVihJNZLvIthvOqYC3JgRqd5SMFPqjj7Q2jWvfWgRJj8KHE2E2T0xTekQpoZiKAgQU7dw== X-Received: by 2002:a1c:6a0d:0:b0:3f4:23d4:e48 with SMTP id f13-20020a1c6a0d000000b003f423d40e48mr18847738wmc.23.1684150301172; Mon, 15 May 2023 04:31:41 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v3 0/2] Add CpuidUserDis support Date: Mon, 15 May 2023 12:31:34 +0100 Message-Id: <20230515113136.2465-1-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 v3: * Move LCAP setters from patch 2 to patch 1 * Comment on rationale for checking CPUID faulting before CpuidUserDis on AMD Nowadays AMD supports trapping the CPUID instruction from ring>0 to ring0, (CpuidUserDis) akin to Intel's "CPUID faulting". There is a difference in that the toggle bit is in a different MSR and the support bit is in CPUID itself rather than yet another MSR. This patch enables AMD hosts to use it when supported in order to provide correct CPUID contents to PV guests. Patch 1 moves vendor-specific code on probe_cpuid_faulting() to amd.c/intel.c Patch 2 adds support for CpuidUserDis, hooking it in the probing path and the context switching path. Alejandro Vallejo (2): x86: Refactor conditional guard in probe_cpuid_faulting() x86: Add support for CpuidUserDis xen/arch/x86/cpu/amd.c | 32 ++++++++++++++++++++- xen/arch/x86/cpu/common.c | 51 ++++++++++++++++++---------------- xen/arch/x86/cpu/intel.c | 12 +++++++- xen/arch/x86/include/asm/amd.h | 1 + 4 files changed, 70 insertions(+), 26 deletions(-)