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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id y9-20020a5d4709000000b00307d58b3da9sm5360033wrq.25.2023.05.26.08.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 May 2023 08:00:47 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 19407304-fbd6-11ed-b230-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1685113248; x=1687705248; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=C28wxsizkvytBc8ueJDeuJt4h314LQLVAiDr/nIoKrw=; b=YAKsBSL5leCDi1kBLrOfpLfnxJcwXqlq2zFIFA9Zmba9uzXgbpEt1/edQBsKeGY2ow jAJKv9jsu3bCh6wCPW4r+CwuZj7GWkDNdndYfs88W59JURSJry7BesL5UWHt5TSuVIaC fKmTIPekn6XJnFVSrzpbEupsoIP2A5EqXOByM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685113248; x=1687705248; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=C28wxsizkvytBc8ueJDeuJt4h314LQLVAiDr/nIoKrw=; b=Euwy6dgJBCVoFPhtsAoR3c5hUER27FwNoJKdNTdHmxEiXSHq/kXNUmTKLTH1VxKExX UkqGZiFP7k/np5VfvfeAZebkChKOBbEYuRnVT84pkyl7Tf3XyjloXi3iJepiZFJHjIcr XRzveKt6mAxJMf/BlowbCC/BVGWdXU5ANGvN/by9Vt7ngpGUnVJ5EDDAYNQG5OFwrJxs QrLmGKNDIgi4H8mLVx+nP1WglyPHiO+Uqo2yhuZHGtQ5SbNJrkFTRoDpAJaxwnexgZvu yXAwZade1QQ7UwSMopTgcyR1UZQwUu47BU3j2WcpwCzAawHSeL0Fw7JbOyq8AORJxIuK Uy2w== X-Gm-Message-State: AC+VfDzp6u5E/GFlFX3+bGNEae1M6LhkAn2/alN5VtAsapqUJlcs9wX2 2aQmQOa3IOrfdPVLVH4lF4HZDoTa5OPDvJcVM+g= X-Google-Smtp-Source: ACHHUZ58CsujQt2FRr6ZgH9ICKzc1N7vEfbKrbuhNPCY2+Ia+n86KmeK3JhFkeKt0m5/h4IAQh4+7Q== X-Received: by 2002:a5d:44c8:0:b0:309:3b8d:16a8 with SMTP id z8-20020a5d44c8000000b003093b8d16a8mr1828847wrr.50.1685113247790; Fri, 26 May 2023 08:00:47 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Wei Liu , Anthony PERARD , Juergen Gross , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 0/3] Add Automatic IBRS support Date: Fri, 26 May 2023 16:00:41 +0100 Message-Id: <20230526150044.31553-1-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Adds support for AMD's Automatic IBRS. It's a set-and-forget feature that prevents lower privileged executions from affecting speculations of higher privileged executions, so retpolines are not required. Furthermore, it clears the RSB upon VMEXIT, so we can avoid doing it if the feature is present. Patch 1 adds the relevant bit definitions for CPUID and EFER. Patch 2 Hooks up AutoIBRS to spec_ctrl. so it's used when IBRS is picked. It also tweaks the heuristics so AutoIBRS is preferred over retpolines as BTI mitigation. This is enough to protect Xen. Patch 3 exposes the feature to HVM guests. Alejandro Vallejo (3): x86: Add bit definitions for Automatic IBRS x86: Add support for AMD's Automatic IBRS x86: Expose Automatic IBRS to guests tools/libs/light/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 + xen/arch/x86/hvm/hvm.c | 3 ++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 4 +- xen/arch/x86/pv/emul-priv-op.c | 4 +- xen/arch/x86/setup.c | 3 ++ xen/arch/x86/smpboot.c | 3 ++ xen/arch/x86/spec_ctrl.c | 52 +++++++++++++++------ xen/include/public/arch-x86/cpufeatureset.h | 1 + 10 files changed, 56 insertions(+), 18 deletions(-)