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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id t6-20020adfe446000000b003179b3fd837sm13699587wrm.33.2023.08.08.06.03.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 06:03:38 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fe04cde5-35eb-11ee-b280-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1691499818; x=1692104618; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=CLQCJAr0rC6dxrW2X+lLr/OB58MmuMcxotnvqWKYPbM=; b=UGPW1p2RXholxwOATeLDNTjmIUchwn+XV6jwctj/fYgqKK2cprRWTt7kO8lOCq50Kp JptcMxuQEndlNW29pSLDdyMxWfWBi5kN1IO51HdLDsnCvjQko6bmZ3RjJEBfvfE4KwDm k8nuNQpdXTr8ju1inovh6r4pp7HOp+O4TxS0Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691499818; x=1692104618; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=CLQCJAr0rC6dxrW2X+lLr/OB58MmuMcxotnvqWKYPbM=; b=CYEZwQi3qXV66D6zEoSorq1VSc1dgCMr36N80wUuobhnjDlMIaHtP0dwvPxGd1DMTP wXovoQPk3NY+pOY+EHYJhCh41HPw+TGjCfN/zezsBbvDzJC4mAGEMLRMLIscJcEDBqjY wpykUNU9kfvD/2fngIXQTAUMVdlXa8UkoO/O3hq+dmAohYxRBwhOubu63tlD78OR0zYW Q+kUWaF4bSGPPEs1/7ZjqeJDSuypwcHyYDkZGNEWrA7565sWbDkmW6WR4p5oHOEa9SHE +5W1rbYxnuDcRfyuNDfq6vYJJLzvFoJSQ6q71AAQKBYOV9sPyi6MOUCGxEmYJcZF46GI cwJg== X-Gm-Message-State: AOJu0YzmH1vA+BhF3rA8j7hQ4NIQ3HrVNaFp++1hFdZn2IFxK0rVC+/p L6U/McBdY+KJA/rzk5vmGIigVjFC+UxNjMusSoU= X-Google-Smtp-Source: AGHT+IFFliAuXIbhDdB6fd04YO90HpZVHVdq6h+VWGjhQ8tReKodm6RNfQoaKVgmVhWpbeJuEFtMdw== X-Received: by 2002:adf:ce90:0:b0:314:3b02:a8a8 with SMTP id r16-20020adfce90000000b003143b02a8a8mr7914781wrn.55.1691499818483; Tue, 08 Aug 2023 06:03:38 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v7 0/3] Prevent attempting updates known to fail Date: Tue, 8 Aug 2023 14:03:28 +0100 Message-Id: <20230808130331.27995-1-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Under certain conditions a CPU may not be able to perform microcode updates even if hardware exists to that effect. In particular: * If Xen runs under certain hypervisors they won't allow microcode updates, and will signal this fact by reporting a microcode revision of -1. * If the DIS_MCU_LOAD bit is set, which is expected in some baremetal clouds where the owner may not trust the tenant, then the CPU is not capable of loading new microcode. This series adds logic so that in both of these cases we don't needlessly attempt updates that are not going to succeed. Patch summary: Patch 1 Ignores microcode facilities when the current microcode revision is -1 Patch 2 Moves the MSR_ARCH_CAPS read in tsx_init() to early_cpu_init() and early_microcode_init() Patch 3 Adds the logic to detect microcode updates being disabled on Intel. Alejandro Vallejo (3): x86/microcode: Ignore microcode loading interface for revision = -1 x86: Read MSR_ARCH_CAPS immediately after early_microcode_init() x86/microcode: Disable microcode update handler if DIS_MCU_UPDATE is set xen/arch/x86/cpu/common.c | 20 ++++++++++---- xen/arch/x86/cpu/microcode/core.c | 38 ++++++++++++++++++++++++--- xen/arch/x86/cpu/microcode/intel.c | 13 +++++++++ xen/arch/x86/cpu/microcode/private.h | 7 +++++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 5 ++++ xen/arch/x86/include/asm/setup.h | 2 +- xen/arch/x86/setup.c | 2 +- xen/arch/x86/tsx.c | 16 +++-------- 9 files changed, 81 insertions(+), 23 deletions(-)