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b=af5q84uBXD8/uwduezc5DlyUBW+hszfgQKabbl1OLjhZNMZ4X4aZZRl1lfayuRuWtx0JXKbNIy0XASpTotxNkr1JckWX2kqMypuNSKWnQr6q4if60a3OLDRale29pVIJOLJvXeYW8MGIuJFLjPCVLM27kFAxgPGfwtGwIoNffR86cX+nRdMfJIcyHcI2G1D0EFBv0fgL6zxopXPte9xBpyH8a4XIRWZCm+6xYeam5wXSFqMoGXLdZmvHpysf3mL+DYnG6xPjscFNzgDEJzVbdxvh3yrzMRI7vVJM7u/a/8IxkF3A7WMtXaaLXcZYXl636nVxhn4AZ3dWlyX4TpsMlg== From: Volodymyr Babchuk To: "xen-devel@lists.xenproject.org" CC: Stewart Hildebrand , Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v1 0/3] ARM: ITS: implement TODO and fix issues with cache Thread-Topic: [PATCH v1 0/3] ARM: ITS: implement TODO and fix issues with cache Thread-Index: AQHZ6ux4FORtu5j2eU+vaSYICEUQjA== Date: Tue, 19 Sep 2023 11:28:53 +0000 Message-ID: <20230919112827.1001484-1-volodymyr_babchuk@epam.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.42.0 x-ms-publictraffictype: Email x-ms-traffictypediagnostic: VI1PR03MB3710:EE_|AS8PR03MB10084:EE_ x-ms-office365-filtering-correlation-id: 9d81a06c-8640-445e-773f-08dbb9039aa3 x-ld-processed: b41b72d0-4e9f-4c26-8a69-f949f367c91d,ExtAddr x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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From user perspective it looks like no interrupts are delivered. I observed those issues when experimented with SR-IOV on Renesas S4 board. In my case it wasn't a 100% reproducible issue, so it took some time and couple of tries to fix it. I wasn't sure if my fix addressed some hardware quirks of S4 board or it was a generic solution, so I postponed publishing of it. Later, Stewart Hildebrand had very simmilar issues with his setup. I shared those 3 patches with him and they fixed his issue as well. So, I believe we need those changes in Xen mainline. Second patch ("ARM: GICv3 ITS: do not invalidate memory while sending a command") is not strictly required, as it just provides a small optimization, but I believe it would be nice to have it in the code base. Volodymyr Babchuk (3): ARM: GICv3 ITS: issue INVALL command after mapping host events ARM: GICv3 ITS: do not invalidate memory while sending a command ARM: GICv3 ITS: flush all buffers, not just command queue xen/arch/arm/gic-v3-its.c | 27 ++++++++++++++++++++++----- xen/arch/arm/include/asm/gic_v3_its.h | 2 +- 2 files changed, 23 insertions(+), 6 deletions(-)