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bh=0BVIA9BD2p8N+4kZSKhtmN3U4mw30lLtB421xQPF2gY=; b=zktDnjjK4babEFP2GuTcm8S894S7w3M5yOA1PG7HR2cQ7K7CEHdZDHK6v5Of02jIZuP1prbOAZK+GtSH2PL0m9zBX4lGHSrjf9ktBnQc4PoRDtsvqIK+zpJHq+tcQAIDPXgCVj1wtVoHJ6s4OL2w79FDmTRiPp0xskXE5qA1L2M= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Stefano Stabellini , Anthony Perard , Paul Durrant , , Huang Rui , Jiqian Chen Subject: [QEMU PATCH v5 0/1] Support device passthrough when dom0 is PVH on Xen Date: Thu, 28 Mar 2024 14:07:30 +0800 Message-ID: <20240328060731.354356-1-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B373:EE_|MW4PR12MB5604:EE_ X-MS-Office365-Filtering-Correlation-Id: 93f91fcf-7979-4d10-0e02-08dc4eed6fca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /ak8AN8NN6XSL8P1NXLbVfOOiJZ7CiHIB0nTU9k4g86Q+PUzOOwZvE8bmDscjty4iM1aN63q96gd7g3G7pQywCxK36yRKEvrKXVyCjYyBK0btGmcn5Rcx8G28VNmPIwi23gy3FZQKGmwH3zJ99d35QBiBxhQLVuHysJYBGLCcDz7TcKn3W6VtELqvV8S6NirO8GCdUbseK0FxEReRnmgW7Lp+uK/05uBoxJ7bSexTzo/KJap/oxWZv5XvbI3H1Fmghhk+KWIWhuSMVkW58omnEswsiUHBI2BHTI7amj8xX95oL3PTQuLVmFq7oV/LcfkiC6FIK9rWFoWBxCVWGrfZ5hGhxNmtWpoAm/Bh59K7Mm3xjRHR+giwO23vPp4TNPIcJSkFsfc7cXb8PVMQSZwSmafTuHgEDwgTcxsWAlpwgwA+eK3QsEett/67fY7jwR2NTgQVO8EXfKy7iTxfD5BMIJoI2+I7NGMXqqLQ7It2jFFyNGQTVOywH2ywnwPWdQ2GOQTtp69ib4yajXtUq1rCZU/q75KEv6lMpenKwuqFPPQwsEJEjdAGjen0XQb5VnNMo1IqI1oT1VubySecQ4OVNXK76ejJZZd5U02nSkSEwaE1Y0JZ9p1LKfqhcI4i2YzLWOMSaV2Emn6VYpCbvhQ3bh0uHuLRPG0+WItDFjGIU3BY4/+9krA/rguuECzg9Yy X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(82310400014)(1800799015)(36860700004)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 06:08:06.9183 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93f91fcf-7979-4d10-0e02-08dc4eed6fca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B373.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5604 Hi All, This is v5 series to support passthrough on Xen when dom0 is PVH. v4->v5 changes: * Add review by Stefano v3->v4 changes: * Add gsi into struct XenHostPCIDevice and use gsi number that read from gsi sysfs if it exists, if there is no gsi sysfs, still use irq. v2->v3 changes: * Du to changes in the implementation of the second patch on kernel side(that adds a new sysfs for gsi instead of a new syscall), so read gsi number from the sysfs of gsi. Below is the description of v2 cover letter: This patch is the v2 of the implementation of passthrough when dom0 is PVH on Xen. Issues we encountered: 1. failed to map pirq for gsi Problem: qemu will call xc_physdev_map_pirq() to map a passthrough device’s gsi to pirq in function xen_pt_realize(). But failed. Reason: According to the implement of xc_physdev_map_pirq(), it needs gsi instead of irq, but qemu pass irq to it and treat irq as gsi, it is got from file /sys/bus/pci/devices/xxxx:xx:xx.x/irq in function xen_host_pci_device_get(). But actually the gsi number is not equal with irq. On PVH dom0, when it allocates irq for a gsi in function acpi_register_gsi_ioapic(), allocation is dynamic, and follow the principle of applying first, distributing first. And if you debug the kernel codes (see function __irq_alloc_descs), you will find the irq number is allocated from small to large by order, but the applying gsi number is not, gsi 38 may come before gsi 28, that causes gsi 38 get a smaller irq number than gsi 28, and then gsi != irq. Solution: we can record the relation between gsi and irq, then when userspace(qemu) want to use gsi, we can do a translation. The third patch of kernel(xen/privcmd: Add new syscall to get gsi from irq) records all the relations in acpi_register_gsi_xen_pvh() when dom0 initialize pci devices, and provide a syscall for userspace to get the gsi from irq. The third patch of xen(tools: Add new function to get gsi from irq) add a new function xc_physdev_gsi_from_irq() to call the new syscall added on kernel side. And then userspace can use that function to get gsi. Then xc_physdev_map_pirq() will success. This v2 on qemu side is the same as the v1 (qemu https://lore.kernel.org/xen-devel/20230312092244.451465-19-ray.huang@amd.com/), just call xc_physdev_gsi_from_irq() to get gsi from irq. Jiqian Chen (1): xen: Use gsi instead of irq for mapping pirq hw/xen/xen-host-pci-device.c | 7 +++++++ hw/xen/xen-host-pci-device.h | 1 + hw/xen/xen_pt.c | 6 +++++- 3 files changed, 13 insertions(+), 1 deletion(-)