From patchwork Wed May 22 22:59:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13671158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DEC82C25B78 for ; Wed, 22 May 2024 22:59:51 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.727903.1132590 (Exim 4.92) (envelope-from ) id 1s9uvq-0007HW-91; Wed, 22 May 2024 22:59:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 727903.1132590; Wed, 22 May 2024 22:59:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s9uvq-0007HP-5q; Wed, 22 May 2024 22:59:38 +0000 Received: by outflank-mailman (input) for mailman id 727903; Wed, 22 May 2024 22:59:37 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s9uvp-0007HJ-At for xen-devel@lists.xenproject.org; Wed, 22 May 2024 22:59:37 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on20600.outbound.protection.outlook.com [2a01:111:f403:200a::600]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id f475f494-188e-11ef-90a1-e314d9c70b13; Thu, 23 May 2024 00:59:35 +0200 (CEST) Received: from MN2PR01CA0060.prod.exchangelabs.com (2603:10b6:208:23f::29) by SJ1PR12MB6265.namprd12.prod.outlook.com (2603:10b6:a03:458::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.20; Wed, 22 May 2024 22:59:31 +0000 Received: from BL6PEPF0001AB53.namprd02.prod.outlook.com (2603:10b6:208:23f:cafe::a8) by MN2PR01CA0060.outlook.office365.com (2603:10b6:208:23f::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7587.36 via Frontend Transport; Wed, 22 May 2024 22:59:30 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by BL6PEPF0001AB53.mail.protection.outlook.com (10.167.241.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7611.14 via Frontend Transport; Wed, 22 May 2024 22:59:30 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 22 May 2024 17:59:30 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 22 May 2024 17:59:29 -0500 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 22 May 2024 17:59:28 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f475f494-188e-11ef-90a1-e314d9c70b13 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kDQVcd/ZyW2nzp4S214UvjpaiC8CuSdExpQblx7tVbT8odBLTxxwLobBYbo2EtjjQdgVhQ103CQIxVTAc3G7USnvvG0Vj6cK/25LqBAGSxebACCnEBhC2MoShrWyqWEXVlrnhBecsABTtt2+Y4ziMnth09/LoPKVHCXvo1iDNSUgchmBOU2qJxcNsdyPkmRa5KaxRe8V6W6CU4rNAULfpEOnTQohiOUXBhUi8TDQ7Ii1QcUljMhHhWLkkM2PloNFDpQevEK1owDY0kCUeBgGU95VdgsWbbxtUi5I/GhGSkU+uPz58eXmML67mm+L2lWc1TSeKXEtG8HVqRlQwexJ0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zTMLUqBpPTGO1t5D5YY5Wm1WqI3sQqiLCW/DYasj35w=; b=OZEZxrrg9LKrtnbG6BeGzcbPcQrZNdWnHpo3CgS6TAdSl7uLZ0uTEfwhz5z9RtSeGZFJWtL6JOJP5sxaD4eOkd9K6rYZ9FJHApp9yAhO8ybU5VDNOA8ab5YfgxM/S71/PDvgAX9KfKExTTqMwPUZzF21PUJ0BJ1+uxqVTrwqQ06rsoZPctv40piY0u4yMgmOVw+0b7BeQ0aeMwimZO8Oi8jVytsBQZ2bisv1jFFHuRpStSfB0JlGuDxu1Ws0ACww4Cv7lZxdr1xDRbE8bc1w57wBp+PFkogarVgN8DtqeHZIIm7lBaiDHcl0j9hXrHTyD8ccR0inRHSmnHizW4lWyA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zTMLUqBpPTGO1t5D5YY5Wm1WqI3sQqiLCW/DYasj35w=; b=b5dPT2VsiUTDKuP3JTZmOt0DigkafYWXDNlZSn/fvRKLbBMrRHTPSIuSpNBM80OpY0AkI+vIuQwRzttCz5pN34yJdpNo1S5wogp3YAFgVR+Mdtde8E8MSWd/5VWdBm5mGeSWIC4t9AJh4fgBt2f1WSYjE16Bu1bp9I0LSvcY+mg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= , Andrew Cooper , "George Dunlap" , Jan Beulich Subject: [PATCH v16 0/5] PCI devices passthrough on Arm, part 3 Date: Wed, 22 May 2024 18:59:19 -0400 Message-ID: <20240522225927.77398-1-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.45.1 MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB53:EE_|SJ1PR12MB6265:EE_ X-MS-Office365-Filtering-Correlation-Id: 686bc822-8494-40b5-f345-08dc7ab2d6be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|82310400017|1800799015|376005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?IrgyqzJlDhm79mj0GV3NpE/NJESBmMO?= =?utf-8?q?Nugaldyy6l+gP3kk187ypMxUOWSB2DZcKSPa6swn/Hv17h7M8Q5o8iFw4ftHvaSJ8?= =?utf-8?q?vsp7jSeRFE+4X0fCo5puWcb24X6GW/7vlG/V+Tm3aaS1Mbp+No7qU4J+/CY4aMDZ2?= =?utf-8?q?Idh3gkqDSiEda6yunIGNptiu9PWwCDD4fRuSd2oLXUqGamrEApXmxfAyq9vlvFGJg?= =?utf-8?q?+aPLBsXcFd8w17poRZgha0YwmQ2Ae/wDDmepogu1cf/mUDc1StUQB4/7n8X13wZSU?= =?utf-8?q?agD+wZDiKSXcCaB/N+s++zaS4kWgmWApOzlwtnjuwWw9pG+XklTFwu/iIWXE27kIy?= =?utf-8?q?hg3MmHAJv6m4hf8r8tdz+dLCbDvZrkRcAPB23bsvwyIcjLtd2EQl1q5cE5Hs5n12v?= =?utf-8?q?o2eE6hf+vUX5/6wbrIZuUXhsDqjYs4PsmXsf5UmmriIpxlYns1/lKtja1nMHUMaDY?= =?utf-8?q?7HJ2jejk/xyGpATM2bGRy1U9JtCXIuwifmnifzTEzoJcgEBywPF4lxJ5ODRd2m++Z?= =?utf-8?q?H18O0djURiCkyWukXq359wedP2KI8jTOX+nQPt5ovUUO8VBERki/pTxPfjOIRx7+E?= =?utf-8?q?DPYfekr08GUNhm/XwoRXZn09szSIrZarBG4gIO00Xph0febsZy8YCnj3eNpUV5glH?= =?utf-8?q?bGhFtgjIkmDX+tAr1k2gyFTO7oxIYglAESFpWgazeURxCD37CWhr1c8k/MLW9bJ7q?= =?utf-8?q?UYTYmSldzXfUT0FEhCxgoFx6sIZXhYY18/Ny6FDghxR7lKEbCZspS3t0yhwoi6zmB?= =?utf-8?q?GEbYG6dUGgnafq4n3Xst5fxfqTcrKiF7PvsjNlYQxP40oxBiu14iqduvDMk0t/QtY?= =?utf-8?q?bBqmypN8If9X/Eamai5ZzrhpzTZBO4RZh1rfL309StiRSls64kAxHmQ6szjq8Sm7G?= =?utf-8?q?tGONRBqbhvTvC4sUAAkZ2EjlypYiUkvtvWQO8WFDYGfVpWs5gA4CM7FQ4P7ZnM2n/?= =?utf-8?q?xfATWU/a8YTEkG46qBFtk4xic6Aw5FjFbzJQ45DtN+M/jpaLYYfPGbmJ4mMTGKbGf?= =?utf-8?q?I60zOB/tVHz8JnmQzQl0JcphUUUWIuxYJ2sheM17ZNGXhK2uCIr9MaWZn0jwBXxou?= =?utf-8?q?zvVGshC1D1lcHM/qNDjnkqfmS4Zej8916hhVSRr573350XQuq18ElBF0iMAGhRvKv?= =?utf-8?q?dkJTWHSq16J4V2t49Mj6BQuQeFJc02G0WfTE/nNN2EeXBtSGZMovKe+KVgQb85bNp?= =?utf-8?q?tiIm/6YTrPFtBqeIe1LX+wRnH0lSNkWCeBwsKk/N5WktIvqp8JDtCqDRJ741NG5vi?= =?utf-8?q?IxAlgFxIxtJOPxkDrJG0rV3nPSBkNiEpBP4SW+MLO/xR1m696DfctpFfs2woAecXb?= =?utf-8?q?qCyfYE37wT51?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(82310400017)(1800799015)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 22:59:30.5060 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 686bc822-8494-40b5-f345-08dc7ab2d6be X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6265 This is next version of vPCI rework. Aim of this series is to prepare ground for introducing PCI support on ARM platform. in v16: - minor updates - see individual patches in v15: - reorder so ("arm/vpci: honor access size when returning an error") comes first in v14: - drop first 9 patches as they were committed - updated ("vpci/header: emulate PCI_COMMAND register for guests") in v13: - drop ("xen/arm: vpci: permit access to guest vpci space") as it was unnecessary in v12: - I (Stewart) coordinated with Volodomyr to send this whole series. So, add my (Stewart) Signed-off-by to all patches. - The biggest change is to re-work the PCI_COMMAND register patch. Additional feedback has also been addressed - see individual patches. - Drop ("pci: msi: pass pdev to pci_enable_msi() function") and ("pci: introduce per-domain PCI rwlock") as they were committed - Rename ("rangeset: add rangeset_empty() function") to ("rangeset: add rangeset_purge() function") - Rename ("vpci/header: rework exit path in init_bars") to ("vpci/header: rework exit path in init_header()") in v11: - Added my (Volodymyr) Signed-off-by tag to all patches - Patch "vpci/header: emulate PCI_COMMAND register for guests" is in intermediate state, because it was agreed to rework it once Stewart's series on register handling are in. - Addressed comments, please see patch descriptions for details. in v10: - Removed patch ("xen/arm: vpci: check guest range"), proper fix for the issue is part of ("vpci/header: emulate PCI_COMMAND register for guests") - Removed patch ("pci/header: reset the command register when adding devices") - Added patch ("rangeset: add rangeset_empty() function") because this function is needed in ("vpci/header: handle p2m range sets per BAR") - Added ("vpci/header: handle p2m range sets per BAR") which addressed an issue discovered by Andrii Chepurnyi during virtio integration - Added ("pci: msi: pass pdev to pci_enable_msi() function"), which is prereq for ("pci: introduce per-domain PCI rwlock") - Fixed "Since v9/v8/... " comments in changelogs to reduce confusion. I left "Since" entries for older versions, because they were added by original author of the patches. in v9: v9 includes addressed commentes from a previous one. Also it introduces a couple patches from Stewart. This patches are related to vPCI use on ARM. Patch "vpci/header: rework exit path in init_bars" was factored-out from "vpci/header: handle p2m range sets per BAR". in v8: The biggest change from previous, mistakenly named, v7 series is how locking is implemented. Instead of d->vpci_rwlock we introduce d->pci_lock which has broader scope, as it protects not only domain's vpci state, but domain's list of PCI devices as well. As we discussed in IRC with Roger, it is not feasible to rework all the existing code to use the new lock right away. It was agreed that any write access to d->pdev_list will be protected by **both** d->pci_lock in write mode and pcidevs_lock(). Read access on other hand should be protected by either d->pci_lock in read mode or pcidevs_lock(). It is expected that existing code will use pcidevs_lock() and new users will use new rw lock. Of course, this does not mean that new users shall not use pcidevs_lock() when it is appropriate. Changes from previous versions are described in each separate patch. Oleksandr Andrushchenko (4): vpci/header: emulate PCI_COMMAND register for guests vpci: add initial support for virtual PCI bus topology xen/arm: translate virtual PCI bus topology for guests xen/arm: account IO handlers for emulated PCI MSI-X Volodymyr Babchuk (1): arm/vpci: honor access size when returning an error xen/arch/arm/vpci.c | 63 +++++++++++++++++++++++------ xen/drivers/Kconfig | 4 ++ xen/drivers/vpci/header.c | 60 +++++++++++++++++++++++++--- xen/drivers/vpci/msi.c | 9 +++++ xen/drivers/vpci/msix.c | 7 ++++ xen/drivers/vpci/vpci.c | 81 ++++++++++++++++++++++++++++++++++++++ xen/include/xen/pci_regs.h | 1 + xen/include/xen/sched.h | 10 ++++- xen/include/xen/vpci.h | 28 +++++++++++++ 9 files changed, 244 insertions(+), 19 deletions(-) base-commit: ced21fbb2842ac4655048bdee56232974ff9ff9c