[0/2] x86: port self-snoop related patches from Linux

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Headers	show Return-Path: <xen-devel-bounces@lists.xenproject.org> From: Jan Beulich <JBeulich@suse.com> To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org> Thread-Topic: [PATCH 0/2] x86: port self-snoop related patches from Linux Thread-Index: AQHVPWCeOVbFKPQYpUu9z2i8gnFCCg== Date: Thu, 18 Jul 2019 12:02:06 +0000 Message-ID: <31d4cb3f-6ff0-a13c-00ce-bced77c6dd78@suse.com> Accept-Language: en-US Content-Language: en-US received-spf: None (protection.outlook.com: suse.com does not designate permitted sender hosts) Content-ID: <5FDA68BFC4663E4FB937807BB0B94A28@namprd18.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: fe9c5b53-00d0-427b-22c3-08d70b77c117 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Jul 2019 12:02:06.6915 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted Subject: [Xen-devel] [PATCH 0/2] x86: port self-snoop related patches from Linux Precedence: list Cc: Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>, =?utf-8?q?Roger_Pau_Monn=C3=A9?= <roger.pau@citrix.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" <xen-devel-bounces@lists.xenproject.org>
Series	x86: port self-snoop related patches from Linux \| expand [0/2] x86: port self-snoop related patches from Linux [1/2] x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata [2/2] x86/mtrr: Skip cache flushes on CPUs with cache self-snooping

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From: Jan Beulich <JBeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Thread-Topic: [PATCH 0/2] x86: port self-snoop related patches from Linux
Thread-Index: AQHVPWCeOVbFKPQYpUu9z2i8gnFCCg==
Date: Thu, 18 Jul 2019 12:02:06 +0000
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Subject: [Xen-devel] [PATCH 0/2] x86: port self-snoop related patches from
 Linux
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Cc: Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>,
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Series

x86: port self-snoop related patches from Linux | expand

Andrew had spotted these going in there, and we clearly want them too. 1: x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata 2: x86/mtrr: Skip cache flushes on CPUs with cache self-snooping Jan