| Message ID | cover.1553935727.git.puwen@hygon.cn (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for Hygon Dhyana Family 18h processor | expand |
On 30/03/2019 10:40, Pu Wen wrote: > As a new x86 CPU vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon) > is a joint venture between AMD and Haiguang Information Technology Co., > Ltd., aims at providing high performance x86 processors for China > server market. > > The first generation Hygon processor(Dhyana) originates from AMD > technology and shares most of the architecture with AMD's family 17h, > but with different CPU vendor ID("HygonGenuine") and family series > number 18h (Hygon negotiated with AMD to make sure that only Hygon > will use family 18h). > > To enable support of Xen to Hygon Dhyana CPU, add a new vendor type > (X86_VENDOR_HYGON, with value of 5), and share most of the code with > AMD family 17h. > > The MSRs and CPUIDs which are used by this patch series are all defined > in this PPR[1]. > > This patch series have been applied and tested successfully on Hygon > Dhyana processor, also been tested on AMD EPYC (family 17h) processor. > It works fine and makes no harm to the existing code. > > Reference: > [1] https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf One thing I don't see in this series is anything about microcode loading. Presumably you'll follow the AMD patchloading mechanism, with a blob you provide yourself? ~Andrew
On 2019/4/2 23:14, Andrew Cooper wrote: > On 30/03/2019 10:40, Pu Wen wrote: >> This patch series have been applied and tested successfully on Hygon >> Dhyana processor, also been tested on AMD EPYC (family 17h) processor. >> It works fine and makes no harm to the existing code. >> >> Reference: >> [1] https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf > > One thing I don't see in this series is anything about microcode Right now Hygon load microcode in BIOS. > loading. Presumably you'll follow the AMD patchloading mechanism, with > a blob you provide yourself? We are exploring the Hygon patchloading mechanism, which will employ most of the functions of AMD's. We also try to make the Hygon microcode blob be compatible with the AMD one. When the Hygon patchloading mechanism is practicable and it's necessary to load the Hygon microcode outside of BIOS, we'll send the patchloading patches to Xen and Linux mailing lists. Thx.
>>> On 02.04.19 at 18:00, <puwen@hygon.cn> wrote: > On 2019/4/2 23:14, Andrew Cooper wrote: >> On 30/03/2019 10:40, Pu Wen wrote: >>> This patch series have been applied and tested successfully on Hygon >>> Dhyana processor, also been tested on AMD EPYC (family 17h) processor. >>> It works fine and makes no harm to the existing code. >>> >>> Reference: >>> [1] > https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh > .pdf >> >> One thing I don't see in this series is anything about microcode > > Right now Hygon load microcode in BIOS. > >> loading. Presumably you'll follow the AMD patchloading mechanism, with >> a blob you provide yourself? > > We are exploring the Hygon patchloading mechanism, which will employ > most of the functions of AMD's. We also try to make the Hygon microcode > blob be compatible with the AMD one. > > When the Hygon patchloading mechanism is practicable and it's necessary > to load the Hygon microcode outside of BIOS, we'll send the patchloading > patches to Xen and Linux mailing lists. I suppose both Intel and AMD had this same intention of ucode loading being a firmware job only, and we see where we are right now. As long as updated firmware does not become available in a timely manner (or perhaps not at all, because of a vendor considering a certain system EOL), there's going to be a need to be able to load it from the OS. Jan
On 2019/4/3 0:15, Jan Beulich wrote: > On 02.04.19 at 18:00, <puwen@hygon.cn> wrote: >> On 2019/4/2 23:14, Andrew Cooper wrote: >>> On 30/03/2019 10:40, Pu Wen wrote: >>>> This patch series have been applied and tested successfully on Hygon >>>> Dhyana processor, also been tested on AMD EPYC (family 17h) processor. >>>> It works fine and makes no harm to the existing code. >>> One thing I don't see in this series is anything about microcode >>> loading. Presumably you'll follow the AMD patchloading mechanism, with >>> a blob you provide yourself? >> When the Hygon patchloading mechanism is practicable and it's necessary >> to load the Hygon microcode outside of BIOS, we'll send the patchloading >> patches to Xen and Linux mailing lists. > > I suppose both Intel and AMD had this same intention of ucode loading > being a firmware job only, and we see where we are right now. As long > as updated firmware does not become available in a timely manner (or > perhaps not at all, because of a vendor considering a certain system > EOL), there's going to be a need to be able to load it from the OS. It's reasonable. But I'll not put the microcode loading patch in this series, and will sent it individually later after sufficiently tested. Or just add Hygon vendor checking to follow the AMD patchloading mechanism right now and do the adjustment for Hygon if needed in the future?
>>> On 03.04.19 at 17:21, <puwen@hygon.cn> wrote: > On 2019/4/3 0:15, Jan Beulich wrote: >> On 02.04.19 at 18:00, <puwen@hygon.cn> wrote: >>> On 2019/4/2 23:14, Andrew Cooper wrote: >>>> On 30/03/2019 10:40, Pu Wen wrote: >>>>> This patch series have been applied and tested successfully on Hygon >>>>> Dhyana processor, also been tested on AMD EPYC (family 17h) processor. >>>>> It works fine and makes no harm to the existing code. >>>> One thing I don't see in this series is anything about microcode >>>> loading. Presumably you'll follow the AMD patchloading mechanism, with >>>> a blob you provide yourself? >>> When the Hygon patchloading mechanism is practicable and it's necessary >>> to load the Hygon microcode outside of BIOS, we'll send the patchloading >>> patches to Xen and Linux mailing lists. >> >> I suppose both Intel and AMD had this same intention of ucode loading >> being a firmware job only, and we see where we are right now. As long >> as updated firmware does not become available in a timely manner (or >> perhaps not at all, because of a vendor considering a certain system >> EOL), there's going to be a need to be able to load it from the OS. > > It's reasonable. But I'll not put the microcode loading patch in this > series, and will sent it individually later after sufficiently tested. Fine with me, but Andrew will speak for himself. > Or just add Hygon vendor checking to follow the AMD patchloading > mechanism right now and do the adjustment for Hygon if needed in the > future? I'd prefer not to see this "blindly" enabled. As you say, it should be tested. If no other changes are needed, the patch will be easy to created and process. Jan
As a new x86 CPU vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon) is a joint venture between AMD and Haiguang Information Technology Co., Ltd., aims at providing high performance x86 processors for China server market. The first generation Hygon processor(Dhyana) originates from AMD technology and shares most of the architecture with AMD's family 17h, but with different CPU vendor ID("HygonGenuine") and family series number 18h (Hygon negotiated with AMD to make sure that only Hygon will use family 18h). To enable support of Xen to Hygon Dhyana CPU, add a new vendor type (X86_VENDOR_HYGON, with value of 5), and share most of the code with AMD family 17h. The MSRs and CPUIDs which are used by this patch series are all defined in this PPR[1]. This patch series have been applied and tested successfully on Hygon Dhyana processor, also been tested on AMD EPYC (family 17h) processor. It works fine and makes no harm to the existing code. Reference: [1] https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf v3->v4: - Revert opt_cpuid_mask_l7s0_(eax/ebx) to amd.c. - Create a separate patch to fix common cpuid faulting probing issue for AMD and Hygon. - Rename _vpmu_init() to common_init() and move the default case into it. - Coding style refine. v2->v3: - Rebased on 4.13-unstable and tested against it. - Simplify code of hygon.c by re-using early_init_amd(). - Return false in the function probe_cpuid_faulting(). - Adjust code for calculating phys_proc_id for Hygon. - Abstract common function _vpmu_init() and add hygon_vpmu_init(). - Refine some comments and descriptions. - Add Acked-by from Jan Beulich for x86/cpu/mtrr, x86/cpu/mce, x86/spec_ctrl, x86/apic, x86/acpi, x86/iommu, x86/pv, x86/domain, x86/domctl and x86/cpuid. v1->v2: - Rebased on 4.12.0-rc3 and tested against it. - Move opt_cpuid_mask_l7s0_(eax/ebx) to common.c. - Insert Hygon cases after AMD ones instead of above. - Remove (rd/wr)msr_hygon_safe and use (rd/wr)msr_safe instead. - Remove wrmsr_hygon and use wrmsrl instead. - Remove the unnecessary change to xstate. - Refine some codes and comments. - Add Acked-by from Jan Beulich for x86/traps. - Add Acked-by from Wei Liu for tools/libxc. Pu Wen (15): x86/cpu: Create Hygon Dhyana architecture support file x86/cpu: Fix common cpuid faulting probing for AMD and Hygon x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2 x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery x86/apic: Add Hygon Dhyana support x86/acpi: Add Hygon Dhyana support x86/iommu: Add Hygon Dhyana support x86/pv: Add Hygon Dhyana support to emulate MSRs access x86/domain: Add Hygon Dhyana support x86/domctl: Add Hygon Dhyana support x86/traps: Add Hygon Dhyana support x86/cpuid: Add Hygon Dhyana support tools/libxc: Add Hygon Dhyana support tools/libxc/xc_cpuid_x86.c | 16 ++++-- xen/arch/x86/acpi/cpu_idle.c | 3 +- xen/arch/x86/acpi/cpufreq/cpufreq.c | 8 +-- xen/arch/x86/acpi/cpufreq/powernow.c | 3 +- xen/arch/x86/apic.c | 5 ++ xen/arch/x86/cpu/Makefile | 1 + xen/arch/x86/cpu/amd.c | 2 +- xen/arch/x86/cpu/common.c | 9 +++- xen/arch/x86/cpu/cpu.h | 3 ++ xen/arch/x86/cpu/hygon.c | 92 ++++++++++++++++++++++++++++++++++ xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 5 +- xen/arch/x86/cpu/mcheck/mce.c | 6 ++- xen/arch/x86/cpu/mcheck/mce_amd.c | 5 +- xen/arch/x86/cpu/mcheck/non-fatal.c | 3 +- xen/arch/x86/cpu/mcheck/vmce.c | 2 + xen/arch/x86/cpu/mtrr/generic.c | 5 +- xen/arch/x86/cpu/vpmu.c | 5 ++ xen/arch/x86/cpu/vpmu_amd.c | 60 +++++++++++++++------- xen/arch/x86/cpuid.c | 10 ++-- xen/arch/x86/dom0_build.c | 3 +- xen/arch/x86/domain.c | 9 ++-- xen/arch/x86/domctl.c | 13 +++-- xen/arch/x86/pv/emul-priv-op.c | 19 ++++--- xen/arch/x86/spec_ctrl.c | 6 ++- xen/arch/x86/traps.c | 3 ++ xen/include/asm-x86/iommu.h | 1 + xen/include/asm-x86/vpmu.h | 1 + xen/include/asm-x86/x86-vendors.h | 3 +- 28 files changed, 244 insertions(+), 57 deletions(-) create mode 100644 xen/arch/x86/cpu/hygon.c