| Message ID | cover.1579615303.git.bobbyeshleman@gmail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | xen: beginning support for RISC-V | expand |
On 22/01/2020 01:58, Bobby Eshleman wrote: > Hey everybody, > > This is an RFC patchset for the very beginnings of adding RISC-V support > to Xen. This RFC is really just to start a dialogue about supporting > RISC-V and align with the Xen project and community before going > further. For that reason, it is very rough and very incomplete. > > My name is Bobby Eshleman, I'm a software engineer at > Star Lab / Wind River on the ARM team, mostly having worked in the Linux > kernel. I've also been involved a good amount with Xen on ARM here, > mostly dealing with tooling, deployment, and testing. A lot of this > patchset is heavily inspired by the Xen/ARM source code (particularly > the early setup up code). > > Currently, this patchset really only sets up virtual memory for Xen and > initializes UART to enable print output. None of RISC-V's > virtualization support has been implemented yet, although that is the > next road to start going down. Many functions only contain dummy > implementations. Many shortcuts have been taken and TODO's have been > left accordingly. It is very, very rough. Be forewarned: you are quite > likely to see some ungainly code here (despite my efforts to clean it up > before sending this patchset out). My intent with this RFC is to align > early and gauge interest, as opposed to presenting a totally complete > patchset. > > Because the ARM and RISC-V use cases will likely bear resemblance, the > RISC-V port should probably respect the design considerations that have > been laid out and respected by Xen on ARM for dom0less, safety > certification, etc... My inclination has been to initially target or > prioritize dom0less (without excluding dom0full) and use the ARM > dom0less implementation as a model to follow. I'd love feedback on this > point and on how the Xen project might envision a RISC-V implementation. > > This patchset has _some_ code for future support for 32-bit, but > currently my focus is on 64-bit. > > Again, this is a very, very rough and totally incomplete patchset. My > goal here is just to gauge community interest, begin discussing what Xen > on RISC-V may look like, receive feedback, and see if I'm heading in the > right direction. > > My big questions are: > Does the Xen project have interest in RISC-V? There is very large downstream interest in RISC-V. So a definite yes. > What can be done to make the RISC-V port as upstreamable as > possible? > Any major pitfalls? > > It would be great to hear all of your feedback. Both RISC-V and Power9 are frequently requested things, and both suffer from the fact that, while we as a community would like them, the upstream intersection of "people who know Xen" and "people who know enough arch $X to do an initial port" is 0. This series clearly demonstrates a change in the status quo, and I think a lot of people will be happy. To get RISC-V to being fully supported, we will ultimately need to get hardware into the CI system, and an easy way for developers to test changes. Do you have any thoughts on production RISC-V hardware (ideally server form factor) for the CI system, and/or dev boards which might be available fairly cheaply? How much time do you have to put towards the port? Is this something in your free time, or something you are doing as part of work? Ultimately, we are going to need to increase the level of RISC-V knowledge in the community to maintain things in the future. Other than that, very RFC series are entirely fine. A good first step would be simply to get the build working, and get some kind of cross-compile build in CI, to make sure that we don't clobber the RISC-V build with common or other-arch changes. I hope this helps. ~Andrew
> On 22 Jan 2020, at 14:57, Andrew Cooper <andrew.cooper3@citrix.com> wrote: > > On 22/01/2020 01:58, Bobby Eshleman wrote: >> Hey everybody, >> >> This is an RFC patchset for the very beginnings of adding RISC-V support >> to Xen. This RFC is really just to start a dialogue about supporting >> RISC-V and align with the Xen project and community before going >> further. For that reason, it is very rough and very incomplete. >> >> My name is Bobby Eshleman, I'm a software engineer at >> Star Lab / Wind River on the ARM team, mostly having worked in the Linux >> kernel. I've also been involved a good amount with Xen on ARM here, >> mostly dealing with tooling, deployment, and testing. A lot of this >> patchset is heavily inspired by the Xen/ARM source code (particularly >> the early setup up code). >> >> Currently, this patchset really only sets up virtual memory for Xen and >> initializes UART to enable print output. None of RISC-V's >> virtualization support has been implemented yet, although that is the >> next road to start going down. Many functions only contain dummy >> implementations. Many shortcuts have been taken and TODO's have been >> left accordingly. It is very, very rough. Be forewarned: you are quite >> likely to see some ungainly code here (despite my efforts to clean it up >> before sending this patchset out). My intent with this RFC is to align >> early and gauge interest, as opposed to presenting a totally complete >> patchset. >> >> Because the ARM and RISC-V use cases will likely bear resemblance, the >> RISC-V port should probably respect the design considerations that have >> been laid out and respected by Xen on ARM for dom0less, safety >> certification, etc... My inclination has been to initially target or >> prioritize dom0less (without excluding dom0full) and use the ARM >> dom0less implementation as a model to follow. I'd love feedback on this >> point and on how the Xen project might envision a RISC-V implementation. >> >> This patchset has _some_ code for future support for 32-bit, but >> currently my focus is on 64-bit. >> >> Again, this is a very, very rough and totally incomplete patchset. My >> goal here is just to gauge community interest, begin discussing what Xen >> on RISC-V may look like, receive feedback, and see if I'm heading in the >> right direction. >> >> My big questions are: >> Does the Xen project have interest in RISC-V? > > There is very large downstream interest in RISC-V. So a definite yes. > >> What can be done to make the RISC-V port as upstreamable as >> possible? >> Any major pitfalls? >> >> It would be great to hear all of your feedback. > > Both RISC-V and Power9 are frequently requested things, and both suffer > from the fact that, while we as a community would like them, the > upstream intersection of "people who know Xen" and "people who know > enough arch $X to do an initial port" is 0. > > This series clearly demonstrates a change in the status quo, and I think > a lot of people will be happy. > > To get RISC-V to being fully supported, we will ultimately need to get > hardware into the CI system, and an easy way for developers to test > changes. Do you have any thoughts on production RISC-V hardware > (ideally server form factor) for the CI system, and/or dev boards which > might be available fairly cheaply? > > How much time do you have to put towards the port? Is this something in > your free time, or something you are doing as part of work? Ultimately, > we are going to need to increase the level of RISC-V knowledge in the > community to maintain things in the future. > > Other than that, very RFC series are entirely fine. A good first step > would be simply to get the build working, and get some kind of > cross-compile build in CI, to make sure that we don't clobber the RISC-V > build with common or other-arch changes. > > I hope this helps. I totally agree with what Andy says. You should also leverage the developer summit: see https://events.linuxfoundation.org/xen-summit/program/cfp/ <https://events.linuxfoundation.org/xen-summit/program/cfp/> CfP closes March 6th. Design sessions can be submitted afterwards Community calls may also be a good option to deal with specific issues / questions, e.g. around compile support in the CI, etc. Lars
On Wed, 22 Jan 2020, Andrew Cooper wrote: > > My big questions are: > > Does the Xen project have interest in RISC-V? > > There is very large downstream interest in RISC-V. So a definite yes. Definite Yes from me too > > What can be done to make the RISC-V port as upstreamable as > > possible? > > Any major pitfalls? > > > > It would be great to hear all of your feedback. > > Both RISC-V and Power9 are frequently requested things, and both suffer > from the fact that, while we as a community would like them, the > upstream intersection of "people who know Xen" and "people who know > enough arch $X to do an initial port" is 0. > > This series clearly demonstrates a change in the status quo, and I think > a lot of people will be happy. > > To get RISC-V to being fully supported, we will ultimately need to get > hardware into the CI system, and an easy way for developers to test > changes. Do you have any thoughts on production RISC-V hardware > (ideally server form factor) for the CI system, and/or dev boards which > might be available fairly cheaply? My understanding is that virtualization development for RISC-V is done on QEMU right now (which could still be hooked into the CI system if somebody wanted to do the work I think.)
On Wed, Jan 22, 2020 at 01:05:11PM -0800, Stefano Stabellini wrote: > On Wed, 22 Jan 2020, Andrew Cooper wrote: > > > My big questions are: > > > Does the Xen project have interest in RISC-V? > > > > There is very large downstream interest in RISC-V. So a definite yes. > > Definite Yes from me too > Both great to hear! > > > > What can be done to make the RISC-V port as upstreamable as > > > possible? > > > Any major pitfalls? > > > > > > It would be great to hear all of your feedback. > > > > Both RISC-V and Power9 are frequently requested things, and both suffer > > from the fact that, while we as a community would like them, the > > upstream intersection of "people who know Xen" and "people who know > > enough arch $X to do an initial port" is 0. > > > > This series clearly demonstrates a change in the status quo, and I think > > a lot of people will be happy. > > > > To get RISC-V to being fully supported, we will ultimately need to get > > hardware into the CI system, and an easy way for developers to test > > changes. Do you have any thoughts on production RISC-V hardware > > (ideally server form factor) for the CI system, and/or dev boards which > > might be available fairly cheaply? > > My understanding is that virtualization development for RISC-V is done > on QEMU right now (which could still be hooked into the CI system if > somebody wanted to do the work I think.) That is correct. I think the RTL and hardware folks are waiting for the spec to be finalized before committing to the effort, so everyone is just developing against QEMU for now. I can certainly look at hooking in QEMU to the CI at some point soon. That is the OSSTest repo, correct?
On Wed, Jan 22, 2020 at 02:57:47PM +0000, Andrew Cooper wrote: > How much time do you have to put towards the port? Is this something in > your free time, or something you are doing as part of work? Ultimately, > we are going to need to increase the level of RISC-V knowledge in the > community to maintain things in the future. > This is something in my free time, and I have about 20 hours a week to put into it. > Other than that, very RFC series are entirely fine. A good first step > would be simply to get the build working, and get some kind of > cross-compile build in CI, to make sure that we don't clobber the RISC-V > build with common or other-arch changes. > That's something I can look at, if the idea of QEMU in CI is not too horrific. > I hope this helps. > > ~Andrew Definitely helps, thanks! -Bobby
On Wed, Jan 22, 2020 at 04:27:39PM +0000, Lars Kurth wrote: > > You should also leverage the developer summit: see https://events.linuxfoundation.org/xen-summit/program/cfp/ <https://events.linuxfoundation.org/xen-summit/program/cfp/> > CfP closes March 6th. Design sessions can be submitted afterwards > > Community calls may also be a good option to deal with specific issues / questions, e.g. around compile support in the CI, etc. > > Lars > That's a really good idea. I'll submit as I do think I can get there if accepted. Thanks for the tip on community calls, I did not realize Xen did those! -Bobby
On Wed, 2020-01-22 at 14:57 +0000, Andrew Cooper wrote: > On 22/01/2020 01:58, Bobby Eshleman wrote: > > Hey everybody, > > > > This is an RFC patchset for the very beginnings of adding RISC-V > > support > > to Xen. This RFC is really just to start a dialogue about > > supporting > > RISC-V and align with the Xen project and community before going > > further. For that reason, it is very rough and very incomplete. > > > > My name is Bobby Eshleman, I'm a software engineer at > > Star Lab / Wind River on the ARM team, mostly having worked in the > > Linux > > kernel. I've also been involved a good amount with Xen on ARM > > here, > > mostly dealing with tooling, deployment, and testing. A lot of > > this > > patchset is heavily inspired by the Xen/ARM source code > > (particularly > > the early setup up code). > > > > Currently, this patchset really only sets up virtual memory for Xen > > and > > initializes UART to enable print output. None of RISC-V's > > virtualization support has been implemented yet, although that is > > the > > next road to start going down. Many functions only contain dummy > > implementations. Many shortcuts have been taken and TODO's have > > been > > left accordingly. It is very, very rough. Be forewarned: you are > > quite > > likely to see some ungainly code here (despite my efforts to clean > > it up > > before sending this patchset out). My intent with this RFC is to > > align > > early and gauge interest, as opposed to presenting a totally > > complete > > patchset. > > > > Because the ARM and RISC-V use cases will likely bear resemblance, > > the > > RISC-V port should probably respect the design considerations that > > have > > been laid out and respected by Xen on ARM for dom0less, safety > > certification, etc... My inclination has been to initially target > > or > > prioritize dom0less (without excluding dom0full) and use the ARM > > dom0less implementation as a model to follow. I'd love feedback on > > this > > point and on how the Xen project might envision a RISC-V > > implementation. > > > > This patchset has _some_ code for future support for 32-bit, but > > currently my focus is on 64-bit. > > > > Again, this is a very, very rough and totally incomplete > > patchset. My > > goal here is just to gauge community interest, begin discussing > > what Xen > > on RISC-V may look like, receive feedback, and see if I'm heading > > in the > > right direction. > > > > My big questions are: > > Does the Xen project have interest in RISC-V? > > There is very large downstream interest in RISC-V. So a definite > yes. > > > What can be done to make the RISC-V port as upstreamable as > > possible? > > Any major pitfalls? > > > > It would be great to hear all of your feedback. > > Both RISC-V and Power9 are frequently requested things, and both > suffer > from the fact that, while we as a community would like them, the > upstream intersection of "people who know Xen" and "people who know > enough arch $X to do an initial port" is 0. > > This series clearly demonstrates a change in the status quo, and I > think > a lot of people will be happy. > > To get RISC-V to being fully supported, we will ultimately need to > get > hardware into the CI system, and an easy way for developers to test > changes. Do you have any thoughts on production RISC-V hardware > (ideally server form factor) for the CI system, and/or dev boards > which > might be available fairly cheaply? AFAIK this is awhile off. The Hypervisor spec is still in a draft state (expecting to be frozen this year) so right now QEMU is the only option. Alistair > > How much time do you have to put towards the port? Is this something > in > your free time, or something you are doing as part of work? > Ultimately, > we are going to need to increase the level of RISC-V knowledge in the > community to maintain things in the future. > > Other than that, very RFC series are entirely fine. A good first > step > would be simply to get the build working, and get some kind of > cross-compile build in CI, to make sure that we don't clobber the > RISC-V > build with common or other-arch changes. > > I hope this helps. > > ~Andrew
On 23/01/2020 05:19, Bobby Eshleman wrote: > On Wed, Jan 22, 2020 at 02:57:47PM +0000, Andrew Cooper wrote: >> How much time do you have to put towards the port? Is this something in >> your free time, or something you are doing as part of work? Ultimately, >> we are going to need to increase the level of RISC-V knowledge in the >> community to maintain things in the future. >> > This is something in my free time, and I have about 20 hours a week to > put into it. Ok, so not full time, but hopefully enough time to help spread some knowledge. > >> Other than that, very RFC series are entirely fine. A good first step >> would be simply to get the build working, and get some kind of >> cross-compile build in CI, to make sure that we don't clobber the RISC-V >> build with common or other-arch changes. >> > That's something I can look at, if the idea of QEMU in CI is > not too horrific. We have https://gitlab.com/xen-project/xen/pipelines which runs a load of containerised builds. How easy is it to set up a containerised RISC-V cross-compiler environment? The test step also boots Xen under Qemu software emulation to check that we don't have any boot-time screamers. A reasonable second step might be to have start_xen() panic() at the end, and check for that in the console log, which would allow for some kind of boot testing before getting all the way to "and here is dom0 ready to run". All configuration is in .gitlab-ci.yml and automation/. ~Andrew
> On 23 Jan 2020, at 05:31, Bobby Eshleman <bobbyeshleman@gmail.com> wrote: > > On Wed, Jan 22, 2020 at 04:27:39PM +0000, Lars Kurth wrote: >> >> You should also leverage the developer summit: see https://events.linuxfoundation.org/xen-summit/program/cfp/ <https://events.linuxfoundation.org/xen-summit/program/cfp/> >> CfP closes March 6th. Design sessions can be submitted afterwards >> >> Community calls may also be a good option to deal with specific issues / questions, e.g. around compile support in the CI, etc. >> >> Lars >> > > That's a really good idea. I'll submit as I do think I can get there if accepted. Thanks for the tip on > community calls, I did not realize Xen did those! > > -Bobby If you add your name/email address to https://cryptpad.fr/pad/#/2/pad/edit/D9vGzihPxxAOe6RFPz0sRCf+/ <https://cryptpad.fr/pad/#/2/pad/edit/D9vGzihPxxAOe6RFPz0sRCf+/> I will CC you on the next invite They are usually the 1st Thursday of each month Past minutes can be found at https://cryptpad.fr/drive/#/2/drive/edit/uZ1UjYxICjse+XlJrXrIwZXN/ Lars
On 22/01/2020 01:58, Bobby Eshleman wrote: > Currently, this patchset really only sets up virtual memory for Xen and > initializes UART to enable print output. None of RISC-V's > virtualization support has been implemented yet, although that is the > next road to start going down. Many functions only contain dummy > implementations. Many shortcuts have been taken and TODO's have been > left accordingly. It is very, very rough. Be forewarned: you are quite > likely to see some ungainly code here (despite my efforts to clean it up > before sending this patchset out). My intent with this RFC is to align > early and gauge interest, as opposed to presenting a totally complete > patchset. I've taken a very quick look over the series. Normally, we require that all patches be bisectable, and this series is not because of the Makefile changes in patch 3 specifying object files which are introduced in the following 20 patches. Of course, introducing a brand new architecture is a special case, but the suggested plan of getting a "minimal build" together will help keep the second phase of "making it boot". To start with, I'd recommend a head.S with _start: and an infinite loop, along with whatever makefile/kconfig infrastructure is required to get a build. Within that first phase however, there are some obvious tweaks we should make to common code. For one, the debugger_trap() infrastructure really is x86-specific (and I haven't seen it used in a decade) so should have its ARM stubs dropped so as not to be a burden on other architectures. There are other aspects (the atomic_t infrastructure) where x86 and ARM already have basically identical copies of the header file, and you've taken a 3rd copy. Other areas where you can reduce the minimum build would be to put some defaults into the defconfig, such as disabling grant tables and mem access. There are almost certainly others which will help, so have a search around menuconfig. Disabling grant tables in particular will work around the fact that the ARM snapshot you based your port on was pre-XSA-295, and the cmpxchg loop against guest memory in gnttab_clear_flags() is reintroducing a previously-fixed security vulnerability. Some ARM-isms you've inherited would be much better if you didn't. In particular, I *really* hope RISC-V hasn't made the same backwards naming bug in their pagetable levels which results in {second,first,zeroth}_* et al. In x86, we purposefully chose not to follow Intel's naming, and instead went with L1, L2, L3, and for 64bit L4. As a couple of general points from our coding style, please avoid commented out code, and you are free to omit braces for single statement blocks. ~Andrew
On Thu, Jan 23, 2020 at 04:02:56PM +0000, Andrew Cooper wrote: > > We have https://gitlab.com/xen-project/xen/pipelines which runs a load > of containerised builds. How easy is it to set up a containerised > RISC-V cross-compiler environment? > It's pretty easy. I personally use a Docker container that has the bins built from source from both the RISC-V gcc toolchain and QEMU. > The test step also boots Xen under Qemu software emulation to check that > we don't have any boot-time screamers. A reasonable second step might > be to have start_xen() panic() at the end, and check for that in the > console log, which would allow for some kind of boot testing before > getting all the way to "and here is dom0 ready to run". > > All configuration is in .gitlab-ci.yml and automation/. > That sounds ideal and like a perfect place to start. Thanks! -Bobby
On Thu, Jan 23, 2020 at 11:44:02PM +0000, Lars Kurth wrote: > If you add your name/email address to https://cryptpad.fr/pad/#/2/pad/edit/D9vGzihPxxAOe6RFPz0sRCf+/ <https://cryptpad.fr/pad/#/2/pad/edit/D9vGzihPxxAOe6RFPz0sRCf+/> I will CC you on the next invite > They are usually the 1st Thursday of each month > Past minutes can be found at https://cryptpad.fr/drive/#/2/drive/edit/uZ1UjYxICjse+XlJrXrIwZXN/ > Lars Done! Thanks. -Bobby
On Fri, Jan 24, 2020 at 01:41:38PM +0000, Andrew Cooper wrote: > On 22/01/2020 01:58, Bobby Eshleman wrote: > > Currently, this patchset really only sets up virtual memory for Xen and > > initializes UART to enable print output. None of RISC-V's > > virtualization support has been implemented yet, although that is the > > next road to start going down. Many functions only contain dummy > > implementations. Many shortcuts have been taken and TODO's have been > > left accordingly. It is very, very rough. Be forewarned: you are quite > > likely to see some ungainly code here (despite my efforts to clean it up > > before sending this patchset out). My intent with this RFC is to align > > early and gauge interest, as opposed to presenting a totally complete > > patchset. > > I've taken a very quick look over the series. > > Normally, we require that all patches be bisectable, and this series is > not because of the Makefile changes in patch 3 specifying object files > which are introduced in the following 20 patches. Of course, > introducing a brand new architecture is a special case, but the > suggested plan of getting a "minimal build" together will help keep the > second phase of "making it boot". That totally makes sense. > > To start with, I'd recommend a head.S with _start: and an infinite loop, > along with whatever makefile/kconfig infrastructure is required to get a > build. > Got it, sounds like a plan. > Within that first phase however, there are some obvious tweaks we should > make to common code. For one, the debugger_trap() infrastructure really > is x86-specific (and I haven't seen it used in a decade) so should have > its ARM stubs dropped so as not to be a burden on other architectures. > > There are other aspects (the atomic_t infrastructure) where x86 and ARM > already have basically identical copies of the header file, and you've > taken a 3rd copy. > > Other areas where you can reduce the minimum build would be to put some > defaults into the defconfig, such as disabling grant tables and mem > access. There are almost certainly others which will help, so have a > search around menuconfig. Taking note of these, I can definitely do that. > > Disabling grant tables in particular will work around the fact that the > ARM snapshot you based your port on was pre-XSA-295, and the cmpxchg > loop against guest memory in gnttab_clear_flags() is reintroducing a > previously-fixed security vulnerability. Duly noted, I'll fix that and look over some of those again and compare them to the newer files, as some are definitely a few version bumps behind. > > Some ARM-isms you've inherited would be much better if you didn't. In > particular, I *really* hope RISC-V hasn't made the same backwards naming > bug in their pagetable levels which results in {second,first,zeroth}_* > et al. In x86, we purposefully chose not to follow Intel's naming, and > instead went with L1, L2, L3, and for 64bit L4. > The RISC-V spec does indeed describe the table level numbers in reverse order: L2 points to L1 points to L0 (for 39bit addresses). For SV48 48bit addresses, it's L3, L2, L1, to L0. That said, in the spec there is no direct mention of LX for levels, and instead these are referred to by the section from the "virtual page number" that they are referred by, (ie VPN[3], VPN[2], etc...). I definitely would not be strongly opposed to this change for a form that reads better. > As a couple of general points from our coding style, please avoid > commented out code, and you are free to omit braces for single statement > blocks. > > ~Andrew Thanks again, -Bobby
On 25/01/2020 03:26, Bobby Eshleman wrote: > On Fri, Jan 24, 2020 at 01:41:38PM +0000, Andrew Cooper wrote: >> On 22/01/2020 01:58, Bobby Eshleman wrote: >>> Currently, this patchset really only sets up virtual memory for Xen and >>> initializes UART to enable print output. None of RISC-V's >>> virtualization support has been implemented yet, although that is the >>> next road to start going down. Many functions only contain dummy >>> implementations. Many shortcuts have been taken and TODO's have been >>> left accordingly. It is very, very rough. Be forewarned: you are quite >>> likely to see some ungainly code here (despite my efforts to clean it up >>> before sending this patchset out). My intent with this RFC is to align >>> early and gauge interest, as opposed to presenting a totally complete >>> patchset. >> I've taken a very quick look over the series. >> >> Normally, we require that all patches be bisectable, and this series is >> not because of the Makefile changes in patch 3 specifying object files >> which are introduced in the following 20 patches. Of course, >> introducing a brand new architecture is a special case, but the >> suggested plan of getting a "minimal build" together will help keep the >> second phase of "making it boot". > That totally makes sense. I see I trailed off in the middle of that final sentence, but it seems I did get my point across. >> Within that first phase however, there are some obvious tweaks we should >> make to common code. For one, the debugger_trap() infrastructure really >> is x86-specific (and I haven't seen it used in a decade) so should have >> its ARM stubs dropped so as not to be a burden on other architectures. >> >> There are other aspects (the atomic_t infrastructure) where x86 and ARM >> already have basically identical copies of the header file, and you've >> taken a 3rd copy. >> >> Other areas where you can reduce the minimum build would be to put some >> defaults into the defconfig, such as disabling grant tables and mem >> access. There are almost certainly others which will help, so have a >> search around menuconfig. > Taking note of these, I can definitely do that. To fore-warn you, there probably will be more things like this which become apparent on further review. While I don't expect you to do all the cleanup (some will almost certainly be quicker for others to do), I would like to take the opportunity to do the obvious bits of cleanup, given the rare opportunity of seeing the minimum viable set of things to make a new arch compile. >> Some ARM-isms you've inherited would be much better if you didn't. In >> particular, I *really* hope RISC-V hasn't made the same backwards naming >> bug in their pagetable levels which results in {second,first,zeroth}_* >> et al. In x86, we purposefully chose not to follow Intel's naming, and >> instead went with L1, L2, L3, and for 64bit L4. > The RISC-V spec does indeed describe the table level numbers in reverse > order: L2 points to L1 points to L0 (for 39bit addresses). > > For SV48 48bit addresses, it's L3, L2, L1, to L0. > > That said, in the spec there is no direct mention of LX for levels, and > instead these are referred to by the section from the "virtual page > number" that they are referred by, (ie VPN[3], VPN[2], etc...). > > I definitely would not be strongly opposed to this change for a form > that reads better. This looks to be the same as what we've chosen to do in x86, give or take a fencepost. I'd recommend using L{3..0} for similarity with the spec (you surely don't want an off-by-one difference between code in Xen and the spec). Whatever you end up choosing, put a description at the top of mm.h (or wherever appropriate) which briefly introduces the terminology in Xen, and cross references any differences with the spec. ~Andrew
On Sat, Jan 25, 2020 at 05:11:18PM +0000, Andrew Cooper wrote: > On 25/01/2020 03:26, Bobby Eshleman wrote: > > On Fri, Jan 24, 2020 at 01:41:38PM +0000, Andrew Cooper wrote: > >> Other areas where you can reduce the minimum build would be to put some > >> defaults into the defconfig, such as disabling grant tables and mem > >> access. There are almost certainly others which will help, so have a > >> search around menuconfig. > > Taking note of these, I can definitely do that. > > To fore-warn you, there probably will be more things like this which > become apparent on further review. > > While I don't expect you to do all the cleanup (some will almost > certainly be quicker for others to do), I would like to take the > opportunity to do the obvious bits of cleanup, given the rare > opportunity of seeing the minimum viable set of things to make a new > arch compile. This sounds very reasonable. > This looks to be the same as what we've chosen to do in x86, give or > take a fencepost. > > I'd recommend using L{3..0} for similarity with the spec (you surely > don't want an off-by-one difference between code in Xen and the spec). > Whatever you end up choosing, put a description at the top of mm.h (or > wherever appropriate) which briefly introduces the terminology in Xen, > and cross references any differences with the spec. Roger that. Thanks again for the feedback. -Bobby
Any updates? I am looking forward to this :-) On Tue, 21 Jan 2020, Bobby Eshleman wrote: > Hey everybody, > > This is an RFC patchset for the very beginnings of adding RISC-V support > to Xen. This RFC is really just to start a dialogue about supporting > RISC-V and align with the Xen project and community before going > further. For that reason, it is very rough and very incomplete. > > My name is Bobby Eshleman, I'm a software engineer at > Star Lab / Wind River on the ARM team, mostly having worked in the Linux > kernel. I've also been involved a good amount with Xen on ARM here, > mostly dealing with tooling, deployment, and testing. A lot of this > patchset is heavily inspired by the Xen/ARM source code (particularly > the early setup up code). > > Currently, this patchset really only sets up virtual memory for Xen and > initializes UART to enable print output. None of RISC-V's > virtualization support has been implemented yet, although that is the > next road to start going down. Many functions only contain dummy > implementations. Many shortcuts have been taken and TODO's have been > left accordingly. It is very, very rough. Be forewarned: you are quite > likely to see some ungainly code here (despite my efforts to clean it up > before sending this patchset out). My intent with this RFC is to align > early and gauge interest, as opposed to presenting a totally complete > patchset. > > Because the ARM and RISC-V use cases will likely bear resemblance, the > RISC-V port should probably respect the design considerations that have > been laid out and respected by Xen on ARM for dom0less, safety > certification, etc... My inclination has been to initially target or > prioritize dom0less (without excluding dom0full) and use the ARM > dom0less implementation as a model to follow. I'd love feedback on this > point and on how the Xen project might envision a RISC-V implementation. > > This patchset has _some_ code for future support for 32-bit, but > currently my focus is on 64-bit. > > Again, this is a very, very rough and totally incomplete patchset. My > goal here is just to gauge community interest, begin discussing what Xen > on RISC-V may look like, receive feedback, and see if I'm heading in the > right direction. > > My big questions are: > Does the Xen project have interest in RISC-V? > What can be done to make the RISC-V port as upstreamable as > possible? > Any major pitfalls? > > It would be great to hear all of your feedback. > > Alistair Francis (20): > HACK: OE Build changes > HACK: Makefile: Don't build Xen tools > riscv: makefiles and Kconfig > riscv: Add riscv to tools/libxc header files > riscv: Add asm-offsets.c > riscv: Add delay.c > riscv: Add domain.c > riscv: Add domctl.c > riscv: Add guestcopy.c > riscv: Add time.c > riscv: Add smp.c > riscv: Add shutdown.c > riscv: Add traps.c > riscv: Add irq.c > riscv: Add vm_event.c > riscv: Add p2m.c > riscv: Add the lib directory > riscv: Add smpboot.c > riscv: Add percpu.c > riscv: Add sysctl.c > > Bobby Eshleman (3): > riscv: header files > riscv: early setup code > riscv: Add iommu.c > > Makefile | 13 +- > config/StdGNU.mk | 12 +- > config/riscv64.mk | 7 + > tools/configure | 32 +- > tools/firmware/Makefile | 12 +- > tools/libxc/include/xenctrl.h | 7 + > tools/libxc/xc_core.h | 2 + > tools/libxc/xc_core_riscv.h | 57 ++ > xen/Makefile | 2 +- > xen/Rules.mk | 2 +- > xen/arch/Kconfig | 1 + > xen/arch/riscv/Kconfig | 36 + > xen/arch/riscv/Makefile | 62 ++ > xen/arch/riscv/Rules.mk | 55 ++ > xen/arch/riscv/asm-offsets.c | 38 + > xen/arch/riscv/configs/riscv32_defconfig | 0 > xen/arch/riscv/configs/riscv64_defconfig | 0 > xen/arch/riscv/delay.c | 114 +++ > xen/arch/riscv/domain.c | 273 +++++++ > xen/arch/riscv/domctl.c | 53 ++ > xen/arch/riscv/guestcopy.c | 158 ++++ > xen/arch/riscv/head.S | 180 +++++ > xen/arch/riscv/irq.c | 107 +++ > xen/arch/riscv/lib/Makefile | 1 + > xen/arch/riscv/lib/find_next_bit.c | 284 +++++++ > xen/arch/riscv/mm.c | 925 +++++++++++++++++++++++ > xen/arch/riscv/p2m.c | 261 +++++++ > xen/arch/riscv/percpu.c | 84 ++ > xen/arch/riscv/platforms/Kconfig | 31 + > xen/arch/riscv/setup.c | 122 +++ > xen/arch/riscv/shutdown.c | 24 + > xen/arch/riscv/smp.c | 41 + > xen/arch/riscv/smpboot.c | 114 +++ > xen/arch/riscv/sysctl.c | 31 + > xen/arch/riscv/time.c | 74 ++ > xen/arch/riscv/traps.c | 56 ++ > xen/arch/riscv/vm_event.c | 42 + > xen/arch/riscv/xen.lds.S | 262 +++++++ > xen/drivers/passthrough/Makefile | 1 + > xen/drivers/passthrough/riscv/Makefile | 1 + > xen/drivers/passthrough/riscv/iommu.c | 74 ++ > xen/include/asm-riscv/altp2m.h | 39 + > xen/include/asm-riscv/asm.h | 76 ++ > xen/include/asm-riscv/atomic.h | 249 ++++++ > xen/include/asm-riscv/bitops.h | 331 ++++++++ > xen/include/asm-riscv/bug.h | 59 ++ > xen/include/asm-riscv/byteorder.h | 16 + > xen/include/asm-riscv/cache.h | 24 + > xen/include/asm-riscv/cmpxchg.h | 382 ++++++++++ > xen/include/asm-riscv/config.h | 203 +++++ > xen/include/asm-riscv/csr.h | 117 +++ > xen/include/asm-riscv/current.h | 50 ++ > xen/include/asm-riscv/debugger.h | 15 + > xen/include/asm-riscv/delay.h | 28 + > xen/include/asm-riscv/desc.h | 12 + > xen/include/asm-riscv/device.h | 15 + > xen/include/asm-riscv/div64.h | 23 + > xen/include/asm-riscv/domain.h | 85 +++ > xen/include/asm-riscv/event.h | 42 + > xen/include/asm-riscv/fence.h | 12 + > xen/include/asm-riscv/flushtlb.h | 56 ++ > xen/include/asm-riscv/grant_table.h | 93 +++ > xen/include/asm-riscv/guest_access.h | 164 ++++ > xen/include/asm-riscv/guest_atomics.h | 62 ++ > xen/include/asm-riscv/hardirq.h | 27 + > xen/include/asm-riscv/hypercall.h | 12 + > xen/include/asm-riscv/init.h | 42 + > xen/include/asm-riscv/io.h | 283 +++++++ > xen/include/asm-riscv/iocap.h | 16 + > xen/include/asm-riscv/iommu.h | 49 ++ > xen/include/asm-riscv/irq.h | 58 ++ > xen/include/asm-riscv/mem_access.h | 35 + > xen/include/asm-riscv/mm.h | 308 ++++++++ > xen/include/asm-riscv/monitor.h | 65 ++ > xen/include/asm-riscv/nospec.h | 25 + > xen/include/asm-riscv/numa.h | 41 + > xen/include/asm-riscv/p2m.h | 410 ++++++++++ > xen/include/asm-riscv/page.h | 327 ++++++++ > xen/include/asm-riscv/paging.h | 16 + > xen/include/asm-riscv/pci.h | 31 + > xen/include/asm-riscv/percpu.h | 34 + > xen/include/asm-riscv/pgtable-bits.h | 53 ++ > xen/include/asm-riscv/processor.h | 60 ++ > xen/include/asm-riscv/random.h | 9 + > xen/include/asm-riscv/regs.h | 42 + > xen/include/asm-riscv/riscv_encoding.h | 682 +++++++++++++++++ > xen/include/asm-riscv/setup.h | 16 + > xen/include/asm-riscv/smp.h | 50 ++ > xen/include/asm-riscv/softirq.h | 16 + > xen/include/asm-riscv/spinlock.h | 13 + > xen/include/asm-riscv/string.h | 28 + > xen/include/asm-riscv/sysregs.h | 14 + > xen/include/asm-riscv/system.h | 96 +++ > xen/include/asm-riscv/time.h | 60 ++ > xen/include/asm-riscv/trace.h | 12 + > xen/include/asm-riscv/types.h | 73 ++ > xen/include/asm-riscv/vm_event.h | 61 ++ > xen/include/asm-riscv/xenoprof.h | 12 + > xen/include/public/arch-riscv.h | 181 +++++ > xen/include/public/arch-riscv/hvm/save.h | 39 + > xen/include/public/hvm/save.h | 2 + > xen/include/public/pmu.h | 2 + > xen/include/public/xen.h | 2 + > 103 files changed, 9064 insertions(+), 42 deletions(-) > create mode 100644 config/riscv64.mk > create mode 100644 tools/libxc/xc_core_riscv.h > create mode 100644 xen/arch/riscv/Kconfig > create mode 100644 xen/arch/riscv/Makefile > create mode 100644 xen/arch/riscv/Rules.mk > create mode 100644 xen/arch/riscv/asm-offsets.c > create mode 100644 xen/arch/riscv/configs/riscv32_defconfig > create mode 100644 xen/arch/riscv/configs/riscv64_defconfig > create mode 100644 xen/arch/riscv/delay.c > create mode 100644 xen/arch/riscv/domain.c > create mode 100644 xen/arch/riscv/domctl.c > create mode 100644 xen/arch/riscv/guestcopy.c > create mode 100644 xen/arch/riscv/head.S > create mode 100644 xen/arch/riscv/irq.c > create mode 100644 xen/arch/riscv/lib/Makefile > create mode 100644 xen/arch/riscv/lib/find_next_bit.c > create mode 100644 xen/arch/riscv/mm.c > create mode 100644 xen/arch/riscv/p2m.c > create mode 100644 xen/arch/riscv/percpu.c > create mode 100644 xen/arch/riscv/platforms/Kconfig > create mode 100644 xen/arch/riscv/setup.c > create mode 100644 xen/arch/riscv/shutdown.c > create mode 100644 xen/arch/riscv/smp.c > create mode 100644 xen/arch/riscv/smpboot.c > create mode 100644 xen/arch/riscv/sysctl.c > create mode 100644 xen/arch/riscv/time.c > create mode 100644 xen/arch/riscv/traps.c > create mode 100644 xen/arch/riscv/vm_event.c > create mode 100644 xen/arch/riscv/xen.lds.S > create mode 100644 xen/drivers/passthrough/riscv/Makefile > create mode 100644 xen/drivers/passthrough/riscv/iommu.c > create mode 100644 xen/include/asm-riscv/altp2m.h > create mode 100644 xen/include/asm-riscv/asm.h > create mode 100644 xen/include/asm-riscv/atomic.h > create mode 100644 xen/include/asm-riscv/bitops.h > create mode 100644 xen/include/asm-riscv/bug.h > create mode 100644 xen/include/asm-riscv/byteorder.h > create mode 100644 xen/include/asm-riscv/cache.h > create mode 100644 xen/include/asm-riscv/cmpxchg.h > create mode 100644 xen/include/asm-riscv/config.h > create mode 100644 xen/include/asm-riscv/csr.h > create mode 100644 xen/include/asm-riscv/current.h > create mode 100644 xen/include/asm-riscv/debugger.h > create mode 100644 xen/include/asm-riscv/delay.h > create mode 100644 xen/include/asm-riscv/desc.h > create mode 100644 xen/include/asm-riscv/device.h > create mode 100644 xen/include/asm-riscv/div64.h > create mode 100644 xen/include/asm-riscv/domain.h > create mode 100644 xen/include/asm-riscv/event.h > create mode 100644 xen/include/asm-riscv/fence.h > create mode 100644 xen/include/asm-riscv/flushtlb.h > create mode 100644 xen/include/asm-riscv/grant_table.h > create mode 100644 xen/include/asm-riscv/guest_access.h > create mode 100644 xen/include/asm-riscv/guest_atomics.h > create mode 100644 xen/include/asm-riscv/hardirq.h > create mode 100644 xen/include/asm-riscv/hypercall.h > create mode 100644 xen/include/asm-riscv/init.h > create mode 100644 xen/include/asm-riscv/io.h > create mode 100644 xen/include/asm-riscv/iocap.h > create mode 100644 xen/include/asm-riscv/iommu.h > create mode 100644 xen/include/asm-riscv/irq.h > create mode 100644 xen/include/asm-riscv/mem_access.h > create mode 100644 xen/include/asm-riscv/mm.h > create mode 100644 xen/include/asm-riscv/monitor.h > create mode 100644 xen/include/asm-riscv/nospec.h > create mode 100644 xen/include/asm-riscv/numa.h > create mode 100644 xen/include/asm-riscv/p2m.h > create mode 100644 xen/include/asm-riscv/page.h > create mode 100644 xen/include/asm-riscv/paging.h > create mode 100644 xen/include/asm-riscv/pci.h > create mode 100644 xen/include/asm-riscv/percpu.h > create mode 100644 xen/include/asm-riscv/pgtable-bits.h > create mode 100644 xen/include/asm-riscv/processor.h > create mode 100644 xen/include/asm-riscv/random.h > create mode 100644 xen/include/asm-riscv/regs.h > create mode 100644 xen/include/asm-riscv/riscv_encoding.h > create mode 100644 xen/include/asm-riscv/setup.h > create mode 100644 xen/include/asm-riscv/smp.h > create mode 100644 xen/include/asm-riscv/softirq.h > create mode 100644 xen/include/asm-riscv/spinlock.h > create mode 100644 xen/include/asm-riscv/string.h > create mode 100644 xen/include/asm-riscv/sysregs.h > create mode 100644 xen/include/asm-riscv/system.h > create mode 100644 xen/include/asm-riscv/time.h > create mode 100644 xen/include/asm-riscv/trace.h > create mode 100644 xen/include/asm-riscv/types.h > create mode 100644 xen/include/asm-riscv/vm_event.h > create mode 100644 xen/include/asm-riscv/xenoprof.h > create mode 100644 xen/include/public/arch-riscv.h > create mode 100644 xen/include/public/arch-riscv/hvm/save.h > > -- > 2.25.0 > > The source code can be found on github: > https://github.com/beshleman/xen/tree/port-to-risc-v > > The patchset only targets the QEMU virt board and it is tested on > Alistair Francis's patchset for QEMU with RISC-V hypervisor extensions > v0.5, found here: > https://github.com/alistair23/qemu/tree/mainline/alistair/riscv-hyp-ext-v0.5.next > > QEMU is built with: > git clone --single-branch --branch mainline/alistair/riscv-hyp-ext-v0.5.next \ > https://github.com/alistair23/qemu.git > cd qemu > mkdir build && cd build > ../configure --target-list=riscv64-softmmu > make -j$(nproc) && make install > > The bootloader used is the standard OpenSBI, built with the command: > CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM=qemu/virt FW_PAYLOAD_PATH=../xen/xen/xen make > > Xen/RISC-V is built with: > XEN_TARGET_ARCH=riscv64 CROSS_COMPILE=riscv64-unknown-linux-gnu- make build > > Xen may be ran with the following command: > qemu-system-riscv64 -cpu rv64,x-h=true -M virt -m 512M -display none \ > -serial stdio -kernel \ > opensbi/build/platform/qemu/virt/firmware/fw_payload.elf > > Also, shoutout to Alistair Francis (from Western Digital) for getting > the ball rolling and doing a ton of the groundwork with > Makefile/Kconfig, a ton of the RISC-V specific header files, and also > the QEMU RISC-V H extension support, and Dan Robertson (a colleague of > mine at Star Lab) for help in forward porting a number of patches that > were out-of-sync with upstream. > > > Thanks, > Bobby Eshleman >
On Mon, Jun 15, 2020 at 6:03 PM Stefano Stabellini <sstabellini@kernel.org> wrote: > > Any updates? I am looking forward to this :-) At the risk of flooding the list with +1s -- I'm also very much looking forward to it! Thanks, Roman. > > > On Tue, 21 Jan 2020, Bobby Eshleman wrote: > > Hey everybody, > > > > This is an RFC patchset for the very beginnings of adding RISC-V support > > to Xen. This RFC is really just to start a dialogue about supporting > > RISC-V and align with the Xen project and community before going > > further. For that reason, it is very rough and very incomplete. > > > > My name is Bobby Eshleman, I'm a software engineer at > > Star Lab / Wind River on the ARM team, mostly having worked in the Linux > > kernel. I've also been involved a good amount with Xen on ARM here, > > mostly dealing with tooling, deployment, and testing. A lot of this > > patchset is heavily inspired by the Xen/ARM source code (particularly > > the early setup up code). > > > > Currently, this patchset really only sets up virtual memory for Xen and > > initializes UART to enable print output. None of RISC-V's > > virtualization support has been implemented yet, although that is the > > next road to start going down. Many functions only contain dummy > > implementations. Many shortcuts have been taken and TODO's have been > > left accordingly. It is very, very rough. Be forewarned: you are quite > > likely to see some ungainly code here (despite my efforts to clean it up > > before sending this patchset out). My intent with this RFC is to align > > early and gauge interest, as opposed to presenting a totally complete > > patchset. > > > > Because the ARM and RISC-V use cases will likely bear resemblance, the > > RISC-V port should probably respect the design considerations that have > > been laid out and respected by Xen on ARM for dom0less, safety > > certification, etc... My inclination has been to initially target or > > prioritize dom0less (without excluding dom0full) and use the ARM > > dom0less implementation as a model to follow. I'd love feedback on this > > point and on how the Xen project might envision a RISC-V implementation. > > > > This patchset has _some_ code for future support for 32-bit, but > > currently my focus is on 64-bit. > > > > Again, this is a very, very rough and totally incomplete patchset. My > > goal here is just to gauge community interest, begin discussing what Xen > > on RISC-V may look like, receive feedback, and see if I'm heading in the > > right direction. > > > > My big questions are: > > Does the Xen project have interest in RISC-V? > > What can be done to make the RISC-V port as upstreamable as > > possible? > > Any major pitfalls? > > > > It would be great to hear all of your feedback. > > > > Alistair Francis (20): > > HACK: OE Build changes > > HACK: Makefile: Don't build Xen tools > > riscv: makefiles and Kconfig > > riscv: Add riscv to tools/libxc header files > > riscv: Add asm-offsets.c > > riscv: Add delay.c > > riscv: Add domain.c > > riscv: Add domctl.c > > riscv: Add guestcopy.c > > riscv: Add time.c > > riscv: Add smp.c > > riscv: Add shutdown.c > > riscv: Add traps.c > > riscv: Add irq.c > > riscv: Add vm_event.c > > riscv: Add p2m.c > > riscv: Add the lib directory > > riscv: Add smpboot.c > > riscv: Add percpu.c > > riscv: Add sysctl.c > > > > Bobby Eshleman (3): > > riscv: header files > > riscv: early setup code > > riscv: Add iommu.c > > > > Makefile | 13 +- > > config/StdGNU.mk | 12 +- > > config/riscv64.mk | 7 + > > tools/configure | 32 +- > > tools/firmware/Makefile | 12 +- > > tools/libxc/include/xenctrl.h | 7 + > > tools/libxc/xc_core.h | 2 + > > tools/libxc/xc_core_riscv.h | 57 ++ > > xen/Makefile | 2 +- > > xen/Rules.mk | 2 +- > > xen/arch/Kconfig | 1 + > > xen/arch/riscv/Kconfig | 36 + > > xen/arch/riscv/Makefile | 62 ++ > > xen/arch/riscv/Rules.mk | 55 ++ > > xen/arch/riscv/asm-offsets.c | 38 + > > xen/arch/riscv/configs/riscv32_defconfig | 0 > > xen/arch/riscv/configs/riscv64_defconfig | 0 > > xen/arch/riscv/delay.c | 114 +++ > > xen/arch/riscv/domain.c | 273 +++++++ > > xen/arch/riscv/domctl.c | 53 ++ > > xen/arch/riscv/guestcopy.c | 158 ++++ > > xen/arch/riscv/head.S | 180 +++++ > > xen/arch/riscv/irq.c | 107 +++ > > xen/arch/riscv/lib/Makefile | 1 + > > xen/arch/riscv/lib/find_next_bit.c | 284 +++++++ > > xen/arch/riscv/mm.c | 925 +++++++++++++++++++++++ > > xen/arch/riscv/p2m.c | 261 +++++++ > > xen/arch/riscv/percpu.c | 84 ++ > > xen/arch/riscv/platforms/Kconfig | 31 + > > xen/arch/riscv/setup.c | 122 +++ > > xen/arch/riscv/shutdown.c | 24 + > > xen/arch/riscv/smp.c | 41 + > > xen/arch/riscv/smpboot.c | 114 +++ > > xen/arch/riscv/sysctl.c | 31 + > > xen/arch/riscv/time.c | 74 ++ > > xen/arch/riscv/traps.c | 56 ++ > > xen/arch/riscv/vm_event.c | 42 + > > xen/arch/riscv/xen.lds.S | 262 +++++++ > > xen/drivers/passthrough/Makefile | 1 + > > xen/drivers/passthrough/riscv/Makefile | 1 + > > xen/drivers/passthrough/riscv/iommu.c | 74 ++ > > xen/include/asm-riscv/altp2m.h | 39 + > > xen/include/asm-riscv/asm.h | 76 ++ > > xen/include/asm-riscv/atomic.h | 249 ++++++ > > xen/include/asm-riscv/bitops.h | 331 ++++++++ > > xen/include/asm-riscv/bug.h | 59 ++ > > xen/include/asm-riscv/byteorder.h | 16 + > > xen/include/asm-riscv/cache.h | 24 + > > xen/include/asm-riscv/cmpxchg.h | 382 ++++++++++ > > xen/include/asm-riscv/config.h | 203 +++++ > > xen/include/asm-riscv/csr.h | 117 +++ > > xen/include/asm-riscv/current.h | 50 ++ > > xen/include/asm-riscv/debugger.h | 15 + > > xen/include/asm-riscv/delay.h | 28 + > > xen/include/asm-riscv/desc.h | 12 + > > xen/include/asm-riscv/device.h | 15 + > > xen/include/asm-riscv/div64.h | 23 + > > xen/include/asm-riscv/domain.h | 85 +++ > > xen/include/asm-riscv/event.h | 42 + > > xen/include/asm-riscv/fence.h | 12 + > > xen/include/asm-riscv/flushtlb.h | 56 ++ > > xen/include/asm-riscv/grant_table.h | 93 +++ > > xen/include/asm-riscv/guest_access.h | 164 ++++ > > xen/include/asm-riscv/guest_atomics.h | 62 ++ > > xen/include/asm-riscv/hardirq.h | 27 + > > xen/include/asm-riscv/hypercall.h | 12 + > > xen/include/asm-riscv/init.h | 42 + > > xen/include/asm-riscv/io.h | 283 +++++++ > > xen/include/asm-riscv/iocap.h | 16 + > > xen/include/asm-riscv/iommu.h | 49 ++ > > xen/include/asm-riscv/irq.h | 58 ++ > > xen/include/asm-riscv/mem_access.h | 35 + > > xen/include/asm-riscv/mm.h | 308 ++++++++ > > xen/include/asm-riscv/monitor.h | 65 ++ > > xen/include/asm-riscv/nospec.h | 25 + > > xen/include/asm-riscv/numa.h | 41 + > > xen/include/asm-riscv/p2m.h | 410 ++++++++++ > > xen/include/asm-riscv/page.h | 327 ++++++++ > > xen/include/asm-riscv/paging.h | 16 + > > xen/include/asm-riscv/pci.h | 31 + > > xen/include/asm-riscv/percpu.h | 34 + > > xen/include/asm-riscv/pgtable-bits.h | 53 ++ > > xen/include/asm-riscv/processor.h | 60 ++ > > xen/include/asm-riscv/random.h | 9 + > > xen/include/asm-riscv/regs.h | 42 + > > xen/include/asm-riscv/riscv_encoding.h | 682 +++++++++++++++++ > > xen/include/asm-riscv/setup.h | 16 + > > xen/include/asm-riscv/smp.h | 50 ++ > > xen/include/asm-riscv/softirq.h | 16 + > > xen/include/asm-riscv/spinlock.h | 13 + > > xen/include/asm-riscv/string.h | 28 + > > xen/include/asm-riscv/sysregs.h | 14 + > > xen/include/asm-riscv/system.h | 96 +++ > > xen/include/asm-riscv/time.h | 60 ++ > > xen/include/asm-riscv/trace.h | 12 + > > xen/include/asm-riscv/types.h | 73 ++ > > xen/include/asm-riscv/vm_event.h | 61 ++ > > xen/include/asm-riscv/xenoprof.h | 12 + > > xen/include/public/arch-riscv.h | 181 +++++ > > xen/include/public/arch-riscv/hvm/save.h | 39 + > > xen/include/public/hvm/save.h | 2 + > > xen/include/public/pmu.h | 2 + > > xen/include/public/xen.h | 2 + > > 103 files changed, 9064 insertions(+), 42 deletions(-) > > create mode 100644 config/riscv64.mk > > create mode 100644 tools/libxc/xc_core_riscv.h > > create mode 100644 xen/arch/riscv/Kconfig > > create mode 100644 xen/arch/riscv/Makefile > > create mode 100644 xen/arch/riscv/Rules.mk > > create mode 100644 xen/arch/riscv/asm-offsets.c > > create mode 100644 xen/arch/riscv/configs/riscv32_defconfig > > create mode 100644 xen/arch/riscv/configs/riscv64_defconfig > > create mode 100644 xen/arch/riscv/delay.c > > create mode 100644 xen/arch/riscv/domain.c > > create mode 100644 xen/arch/riscv/domctl.c > > create mode 100644 xen/arch/riscv/guestcopy.c > > create mode 100644 xen/arch/riscv/head.S > > create mode 100644 xen/arch/riscv/irq.c > > create mode 100644 xen/arch/riscv/lib/Makefile > > create mode 100644 xen/arch/riscv/lib/find_next_bit.c > > create mode 100644 xen/arch/riscv/mm.c > > create mode 100644 xen/arch/riscv/p2m.c > > create mode 100644 xen/arch/riscv/percpu.c > > create mode 100644 xen/arch/riscv/platforms/Kconfig > > create mode 100644 xen/arch/riscv/setup.c > > create mode 100644 xen/arch/riscv/shutdown.c > > create mode 100644 xen/arch/riscv/smp.c > > create mode 100644 xen/arch/riscv/smpboot.c > > create mode 100644 xen/arch/riscv/sysctl.c > > create mode 100644 xen/arch/riscv/time.c > > create mode 100644 xen/arch/riscv/traps.c > > create mode 100644 xen/arch/riscv/vm_event.c > > create mode 100644 xen/arch/riscv/xen.lds.S > > create mode 100644 xen/drivers/passthrough/riscv/Makefile > > create mode 100644 xen/drivers/passthrough/riscv/iommu.c > > create mode 100644 xen/include/asm-riscv/altp2m.h > > create mode 100644 xen/include/asm-riscv/asm.h > > create mode 100644 xen/include/asm-riscv/atomic.h > > create mode 100644 xen/include/asm-riscv/bitops.h > > create mode 100644 xen/include/asm-riscv/bug.h > > create mode 100644 xen/include/asm-riscv/byteorder.h > > create mode 100644 xen/include/asm-riscv/cache.h > > create mode 100644 xen/include/asm-riscv/cmpxchg.h > > create mode 100644 xen/include/asm-riscv/config.h > > create mode 100644 xen/include/asm-riscv/csr.h > > create mode 100644 xen/include/asm-riscv/current.h > > create mode 100644 xen/include/asm-riscv/debugger.h > > create mode 100644 xen/include/asm-riscv/delay.h > > create mode 100644 xen/include/asm-riscv/desc.h > > create mode 100644 xen/include/asm-riscv/device.h > > create mode 100644 xen/include/asm-riscv/div64.h > > create mode 100644 xen/include/asm-riscv/domain.h > > create mode 100644 xen/include/asm-riscv/event.h > > create mode 100644 xen/include/asm-riscv/fence.h > > create mode 100644 xen/include/asm-riscv/flushtlb.h > > create mode 100644 xen/include/asm-riscv/grant_table.h > > create mode 100644 xen/include/asm-riscv/guest_access.h > > create mode 100644 xen/include/asm-riscv/guest_atomics.h > > create mode 100644 xen/include/asm-riscv/hardirq.h > > create mode 100644 xen/include/asm-riscv/hypercall.h > > create mode 100644 xen/include/asm-riscv/init.h > > create mode 100644 xen/include/asm-riscv/io.h > > create mode 100644 xen/include/asm-riscv/iocap.h > > create mode 100644 xen/include/asm-riscv/iommu.h > > create mode 100644 xen/include/asm-riscv/irq.h > > create mode 100644 xen/include/asm-riscv/mem_access.h > > create mode 100644 xen/include/asm-riscv/mm.h > > create mode 100644 xen/include/asm-riscv/monitor.h > > create mode 100644 xen/include/asm-riscv/nospec.h > > create mode 100644 xen/include/asm-riscv/numa.h > > create mode 100644 xen/include/asm-riscv/p2m.h > > create mode 100644 xen/include/asm-riscv/page.h > > create mode 100644 xen/include/asm-riscv/paging.h > > create mode 100644 xen/include/asm-riscv/pci.h > > create mode 100644 xen/include/asm-riscv/percpu.h > > create mode 100644 xen/include/asm-riscv/pgtable-bits.h > > create mode 100644 xen/include/asm-riscv/processor.h > > create mode 100644 xen/include/asm-riscv/random.h > > create mode 100644 xen/include/asm-riscv/regs.h > > create mode 100644 xen/include/asm-riscv/riscv_encoding.h > > create mode 100644 xen/include/asm-riscv/setup.h > > create mode 100644 xen/include/asm-riscv/smp.h > > create mode 100644 xen/include/asm-riscv/softirq.h > > create mode 100644 xen/include/asm-riscv/spinlock.h > > create mode 100644 xen/include/asm-riscv/string.h > > create mode 100644 xen/include/asm-riscv/sysregs.h > > create mode 100644 xen/include/asm-riscv/system.h > > create mode 100644 xen/include/asm-riscv/time.h > > create mode 100644 xen/include/asm-riscv/trace.h > > create mode 100644 xen/include/asm-riscv/types.h > > create mode 100644 xen/include/asm-riscv/vm_event.h > > create mode 100644 xen/include/asm-riscv/xenoprof.h > > create mode 100644 xen/include/public/arch-riscv.h > > create mode 100644 xen/include/public/arch-riscv/hvm/save.h > > > > -- > > 2.25.0 > > > > The source code can be found on github: > > https://github.com/beshleman/xen/tree/port-to-risc-v > > > > The patchset only targets the QEMU virt board and it is tested on > > Alistair Francis's patchset for QEMU with RISC-V hypervisor extensions > > v0.5, found here: > > https://github.com/alistair23/qemu/tree/mainline/alistair/riscv-hyp-ext-v0.5.next > > > > QEMU is built with: > > git clone --single-branch --branch mainline/alistair/riscv-hyp-ext-v0.5.next \ > > https://github.com/alistair23/qemu.git > > cd qemu > > mkdir build && cd build > > ../configure --target-list=riscv64-softmmu > > make -j$(nproc) && make install > > > > The bootloader used is the standard OpenSBI, built with the command: > > CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM=qemu/virt FW_PAYLOAD_PATH=../xen/xen/xen make > > > > Xen/RISC-V is built with: > > XEN_TARGET_ARCH=riscv64 CROSS_COMPILE=riscv64-unknown-linux-gnu- make build > > > > Xen may be ran with the following command: > > qemu-system-riscv64 -cpu rv64,x-h=true -M virt -m 512M -display none \ > > -serial stdio -kernel \ > > opensbi/build/platform/qemu/virt/firmware/fw_payload.elf > > > > Also, shoutout to Alistair Francis (from Western Digital) for getting > > the ball rolling and doing a ton of the groundwork with > > Makefile/Kconfig, a ton of the RISC-V specific header files, and also > > the QEMU RISC-V H extension support, and Dan Robertson (a colleague of > > mine at Star Lab) for help in forward porting a number of patches that > > were out-of-sync with upstream. > > > > > > Thanks, > > Bobby Eshleman > > >
On Mon, 2020-06-15 at 18:03 -0700, Stefano Stabellini wrote: > Any updates? I am looking forward to this :-) FYI, I would like to talk more about RISC-V Xen at the Xen Virtual summit. I'll put it forward as a BoF subject. I haven't worked on this, although the RISC-V Hypervisor spec is progressing towards ratification. Alistair > > > On Tue, 21 Jan 2020, Bobby Eshleman wrote: > > Hey everybody, > > > > This is an RFC patchset for the very beginnings of adding RISC-V > > support > > to Xen. This RFC is really just to start a dialogue about > > supporting > > RISC-V and align with the Xen project and community before going > > further. For that reason, it is very rough and very incomplete. > > > > My name is Bobby Eshleman, I'm a software engineer at > > Star Lab / Wind River on the ARM team, mostly having worked in the > > Linux > > kernel. I've also been involved a good amount with Xen on ARM > > here, > > mostly dealing with tooling, deployment, and testing. A lot of > > this > > patchset is heavily inspired by the Xen/ARM source code > > (particularly > > the early setup up code). > > > > Currently, this patchset really only sets up virtual memory for Xen > > and > > initializes UART to enable print output. None of RISC-V's > > virtualization support has been implemented yet, although that is > > the > > next road to start going down. Many functions only contain dummy > > implementations. Many shortcuts have been taken and TODO's have > > been > > left accordingly. It is very, very rough. Be forewarned: you are > > quite > > likely to see some ungainly code here (despite my efforts to clean > > it up > > before sending this patchset out). My intent with this RFC is to > > align > > early and gauge interest, as opposed to presenting a totally > > complete > > patchset. > > > > Because the ARM and RISC-V use cases will likely bear resemblance, > > the > > RISC-V port should probably respect the design considerations that > > have > > been laid out and respected by Xen on ARM for dom0less, safety > > certification, etc... My inclination has been to initially target > > or > > prioritize dom0less (without excluding dom0full) and use the ARM > > dom0less implementation as a model to follow. I'd love feedback on > > this > > point and on how the Xen project might envision a RISC-V > > implementation. > > > > This patchset has _some_ code for future support for 32-bit, but > > currently my focus is on 64-bit. > > > > Again, this is a very, very rough and totally incomplete > > patchset. My > > goal here is just to gauge community interest, begin discussing > > what Xen > > on RISC-V may look like, receive feedback, and see if I'm heading > > in the > > right direction. > > > > My big questions are: > > Does the Xen project have interest in RISC-V? > > What can be done to make the RISC-V port as upstreamable as > > possible? > > Any major pitfalls? > > > > It would be great to hear all of your feedback. > > > > Alistair Francis (20): > > HACK: OE Build changes > > HACK: Makefile: Don't build Xen tools > > riscv: makefiles and Kconfig > > riscv: Add riscv to tools/libxc header files > > riscv: Add asm-offsets.c > > riscv: Add delay.c > > riscv: Add domain.c > > riscv: Add domctl.c > > riscv: Add guestcopy.c > > riscv: Add time.c > > riscv: Add smp.c > > riscv: Add shutdown.c > > riscv: Add traps.c > > riscv: Add irq.c > > riscv: Add vm_event.c > > riscv: Add p2m.c > > riscv: Add the lib directory > > riscv: Add smpboot.c > > riscv: Add percpu.c > > riscv: Add sysctl.c > > > > Bobby Eshleman (3): > > riscv: header files > > riscv: early setup code > > riscv: Add iommu.c > > > > Makefile | 13 +- > > config/StdGNU.mk | 12 +- > > config/riscv64.mk | 7 + > > tools/configure | 32 +- > > tools/firmware/Makefile | 12 +- > > tools/libxc/include/xenctrl.h | 7 + > > tools/libxc/xc_core.h | 2 + > > tools/libxc/xc_core_riscv.h | 57 ++ > > xen/Makefile | 2 +- > > xen/Rules.mk | 2 +- > > xen/arch/Kconfig | 1 + > > xen/arch/riscv/Kconfig | 36 + > > xen/arch/riscv/Makefile | 62 ++ > > xen/arch/riscv/Rules.mk | 55 ++ > > xen/arch/riscv/asm-offsets.c | 38 + > > xen/arch/riscv/configs/riscv32_defconfig | 0 > > xen/arch/riscv/configs/riscv64_defconfig | 0 > > xen/arch/riscv/delay.c | 114 +++ > > xen/arch/riscv/domain.c | 273 +++++++ > > xen/arch/riscv/domctl.c | 53 ++ > > xen/arch/riscv/guestcopy.c | 158 ++++ > > xen/arch/riscv/head.S | 180 +++++ > > xen/arch/riscv/irq.c | 107 +++ > > xen/arch/riscv/lib/Makefile | 1 + > > xen/arch/riscv/lib/find_next_bit.c | 284 +++++++ > > xen/arch/riscv/mm.c | 925 > > +++++++++++++++++++++++ > > xen/arch/riscv/p2m.c | 261 +++++++ > > xen/arch/riscv/percpu.c | 84 ++ > > xen/arch/riscv/platforms/Kconfig | 31 + > > xen/arch/riscv/setup.c | 122 +++ > > xen/arch/riscv/shutdown.c | 24 + > > xen/arch/riscv/smp.c | 41 + > > xen/arch/riscv/smpboot.c | 114 +++ > > xen/arch/riscv/sysctl.c | 31 + > > xen/arch/riscv/time.c | 74 ++ > > xen/arch/riscv/traps.c | 56 ++ > > xen/arch/riscv/vm_event.c | 42 + > > xen/arch/riscv/xen.lds.S | 262 +++++++ > > xen/drivers/passthrough/Makefile | 1 + > > xen/drivers/passthrough/riscv/Makefile | 1 + > > xen/drivers/passthrough/riscv/iommu.c | 74 ++ > > xen/include/asm-riscv/altp2m.h | 39 + > > xen/include/asm-riscv/asm.h | 76 ++ > > xen/include/asm-riscv/atomic.h | 249 ++++++ > > xen/include/asm-riscv/bitops.h | 331 ++++++++ > > xen/include/asm-riscv/bug.h | 59 ++ > > xen/include/asm-riscv/byteorder.h | 16 + > > xen/include/asm-riscv/cache.h | 24 + > > xen/include/asm-riscv/cmpxchg.h | 382 ++++++++++ > > xen/include/asm-riscv/config.h | 203 +++++ > > xen/include/asm-riscv/csr.h | 117 +++ > > xen/include/asm-riscv/current.h | 50 ++ > > xen/include/asm-riscv/debugger.h | 15 + > > xen/include/asm-riscv/delay.h | 28 + > > xen/include/asm-riscv/desc.h | 12 + > > xen/include/asm-riscv/device.h | 15 + > > xen/include/asm-riscv/div64.h | 23 + > > xen/include/asm-riscv/domain.h | 85 +++ > > xen/include/asm-riscv/event.h | 42 + > > xen/include/asm-riscv/fence.h | 12 + > > xen/include/asm-riscv/flushtlb.h | 56 ++ > > xen/include/asm-riscv/grant_table.h | 93 +++ > > xen/include/asm-riscv/guest_access.h | 164 ++++ > > xen/include/asm-riscv/guest_atomics.h | 62 ++ > > xen/include/asm-riscv/hardirq.h | 27 + > > xen/include/asm-riscv/hypercall.h | 12 + > > xen/include/asm-riscv/init.h | 42 + > > xen/include/asm-riscv/io.h | 283 +++++++ > > xen/include/asm-riscv/iocap.h | 16 + > > xen/include/asm-riscv/iommu.h | 49 ++ > > xen/include/asm-riscv/irq.h | 58 ++ > > xen/include/asm-riscv/mem_access.h | 35 + > > xen/include/asm-riscv/mm.h | 308 ++++++++ > > xen/include/asm-riscv/monitor.h | 65 ++ > > xen/include/asm-riscv/nospec.h | 25 + > > xen/include/asm-riscv/numa.h | 41 + > > xen/include/asm-riscv/p2m.h | 410 ++++++++++ > > xen/include/asm-riscv/page.h | 327 ++++++++ > > xen/include/asm-riscv/paging.h | 16 + > > xen/include/asm-riscv/pci.h | 31 + > > xen/include/asm-riscv/percpu.h | 34 + > > xen/include/asm-riscv/pgtable-bits.h | 53 ++ > > xen/include/asm-riscv/processor.h | 60 ++ > > xen/include/asm-riscv/random.h | 9 + > > xen/include/asm-riscv/regs.h | 42 + > > xen/include/asm-riscv/riscv_encoding.h | 682 +++++++++++++++++ > > xen/include/asm-riscv/setup.h | 16 + > > xen/include/asm-riscv/smp.h | 50 ++ > > xen/include/asm-riscv/softirq.h | 16 + > > xen/include/asm-riscv/spinlock.h | 13 + > > xen/include/asm-riscv/string.h | 28 + > > xen/include/asm-riscv/sysregs.h | 14 + > > xen/include/asm-riscv/system.h | 96 +++ > > xen/include/asm-riscv/time.h | 60 ++ > > xen/include/asm-riscv/trace.h | 12 + > > xen/include/asm-riscv/types.h | 73 ++ > > xen/include/asm-riscv/vm_event.h | 61 ++ > > xen/include/asm-riscv/xenoprof.h | 12 + > > xen/include/public/arch-riscv.h | 181 +++++ > > xen/include/public/arch-riscv/hvm/save.h | 39 + > > xen/include/public/hvm/save.h | 2 + > > xen/include/public/pmu.h | 2 + > > xen/include/public/xen.h | 2 + > > 103 files changed, 9064 insertions(+), 42 deletions(-) > > create mode 100644 config/riscv64.mk > > create mode 100644 tools/libxc/xc_core_riscv.h > > create mode 100644 xen/arch/riscv/Kconfig > > create mode 100644 xen/arch/riscv/Makefile > > create mode 100644 xen/arch/riscv/Rules.mk > > create mode 100644 xen/arch/riscv/asm-offsets.c > > create mode 100644 xen/arch/riscv/configs/riscv32_defconfig > > create mode 100644 xen/arch/riscv/configs/riscv64_defconfig > > create mode 100644 xen/arch/riscv/delay.c > > create mode 100644 xen/arch/riscv/domain.c > > create mode 100644 xen/arch/riscv/domctl.c > > create mode 100644 xen/arch/riscv/guestcopy.c > > create mode 100644 xen/arch/riscv/head.S > > create mode 100644 xen/arch/riscv/irq.c > > create mode 100644 xen/arch/riscv/lib/Makefile > > create mode 100644 xen/arch/riscv/lib/find_next_bit.c > > create mode 100644 xen/arch/riscv/mm.c > > create mode 100644 xen/arch/riscv/p2m.c > > create mode 100644 xen/arch/riscv/percpu.c > > create mode 100644 xen/arch/riscv/platforms/Kconfig > > create mode 100644 xen/arch/riscv/setup.c > > create mode 100644 xen/arch/riscv/shutdown.c > > create mode 100644 xen/arch/riscv/smp.c > > create mode 100644 xen/arch/riscv/smpboot.c > > create mode 100644 xen/arch/riscv/sysctl.c > > create mode 100644 xen/arch/riscv/time.c > > create mode 100644 xen/arch/riscv/traps.c > > create mode 100644 xen/arch/riscv/vm_event.c > > create mode 100644 xen/arch/riscv/xen.lds.S > > create mode 100644 xen/drivers/passthrough/riscv/Makefile > > create mode 100644 xen/drivers/passthrough/riscv/iommu.c > > create mode 100644 xen/include/asm-riscv/altp2m.h > > create mode 100644 xen/include/asm-riscv/asm.h > > create mode 100644 xen/include/asm-riscv/atomic.h > > create mode 100644 xen/include/asm-riscv/bitops.h > > create mode 100644 xen/include/asm-riscv/bug.h > > create mode 100644 xen/include/asm-riscv/byteorder.h > > create mode 100644 xen/include/asm-riscv/cache.h > > create mode 100644 xen/include/asm-riscv/cmpxchg.h > > create mode 100644 xen/include/asm-riscv/config.h > > create mode 100644 xen/include/asm-riscv/csr.h > > create mode 100644 xen/include/asm-riscv/current.h > > create mode 100644 xen/include/asm-riscv/debugger.h > > create mode 100644 xen/include/asm-riscv/delay.h > > create mode 100644 xen/include/asm-riscv/desc.h > > create mode 100644 xen/include/asm-riscv/device.h > > create mode 100644 xen/include/asm-riscv/div64.h > > create mode 100644 xen/include/asm-riscv/domain.h > > create mode 100644 xen/include/asm-riscv/event.h > > create mode 100644 xen/include/asm-riscv/fence.h > > create mode 100644 xen/include/asm-riscv/flushtlb.h > > create mode 100644 xen/include/asm-riscv/grant_table.h > > create mode 100644 xen/include/asm-riscv/guest_access.h > > create mode 100644 xen/include/asm-riscv/guest_atomics.h > > create mode 100644 xen/include/asm-riscv/hardirq.h > > create mode 100644 xen/include/asm-riscv/hypercall.h > > create mode 100644 xen/include/asm-riscv/init.h > > create mode 100644 xen/include/asm-riscv/io.h > > create mode 100644 xen/include/asm-riscv/iocap.h > > create mode 100644 xen/include/asm-riscv/iommu.h > > create mode 100644 xen/include/asm-riscv/irq.h > > create mode 100644 xen/include/asm-riscv/mem_access.h > > create mode 100644 xen/include/asm-riscv/mm.h > > create mode 100644 xen/include/asm-riscv/monitor.h > > create mode 100644 xen/include/asm-riscv/nospec.h > > create mode 100644 xen/include/asm-riscv/numa.h > > create mode 100644 xen/include/asm-riscv/p2m.h > > create mode 100644 xen/include/asm-riscv/page.h > > create mode 100644 xen/include/asm-riscv/paging.h > > create mode 100644 xen/include/asm-riscv/pci.h > > create mode 100644 xen/include/asm-riscv/percpu.h > > create mode 100644 xen/include/asm-riscv/pgtable-bits.h > > create mode 100644 xen/include/asm-riscv/processor.h > > create mode 100644 xen/include/asm-riscv/random.h > > create mode 100644 xen/include/asm-riscv/regs.h > > create mode 100644 xen/include/asm-riscv/riscv_encoding.h > > create mode 100644 xen/include/asm-riscv/setup.h > > create mode 100644 xen/include/asm-riscv/smp.h > > create mode 100644 xen/include/asm-riscv/softirq.h > > create mode 100644 xen/include/asm-riscv/spinlock.h > > create mode 100644 xen/include/asm-riscv/string.h > > create mode 100644 xen/include/asm-riscv/sysregs.h > > create mode 100644 xen/include/asm-riscv/system.h > > create mode 100644 xen/include/asm-riscv/time.h > > create mode 100644 xen/include/asm-riscv/trace.h > > create mode 100644 xen/include/asm-riscv/types.h > > create mode 100644 xen/include/asm-riscv/vm_event.h > > create mode 100644 xen/include/asm-riscv/xenoprof.h > > create mode 100644 xen/include/public/arch-riscv.h > > create mode 100644 xen/include/public/arch-riscv/hvm/save.h > > > > -- > > 2.25.0 > > > > The source code can be found on github: > > https://github.com/beshleman/xen/tree/port-to-risc-v > > > > The patchset only targets the QEMU virt board and it is tested on > > Alistair Francis's patchset for QEMU with RISC-V hypervisor > > extensions > > v0.5, found here: > > > > https://github.com/alistair23/qemu/tree/mainline/alistair/riscv-hyp-ext-v0.5.next > > > > QEMU is built with: > > git clone --single-branch --branch mainline/alistair/riscv-hyp- > > ext-v0.5.next \ > > https://github.com/alistair23/qemu.git > > cd qemu > > mkdir build && cd build > > ../configure --target-list=riscv64-softmmu > > make -j$(nproc) && make install > > > > The bootloader used is the standard OpenSBI, built with the > > command: > > CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM=qemu/virt > > FW_PAYLOAD_PATH=../xen/xen/xen make > > > > Xen/RISC-V is built with: > > XEN_TARGET_ARCH=riscv64 CROSS_COMPILE=riscv64-unknown-linux- > > gnu- make build > > > > Xen may be ran with the following command: > > qemu-system-riscv64 -cpu rv64,x-h=true -M virt -m 512M -display > > none \ > > -serial stdio -kernel \ > > opensbi/build/platform/qemu/virt/firmware/fw_payload.el > > f > > > > Also, shoutout to Alistair Francis (from Western Digital) for > > getting > > the ball rolling and doing a ton of the groundwork with > > Makefile/Kconfig, a ton of the RISC-V specific header files, and > > also > > the QEMU RISC-V H extension support, and Dan Robertson (a colleague > > of > > mine at Star Lab) for help in forward porting a number of patches > > that > > were out-of-sync with upstream. > > > > > > Thanks, > > Bobby Eshleman > >
On Tue, Jun 16, 2020 at 01:10:17AM +0000, Alistair Francis wrote: > On Mon, 2020-06-15 at 18:03 -0700, Stefano Stabellini wrote: > > Any updates? I am looking forward to this :-) > It has been on a slow burn since I became a new dad (shortly after the RFC). I've gradually regained free time, and so I've been able to change that slow burn to a moderate burn in the last couple weeks. Most of my progress has been around build environment improvements. I've done some work stripping it down to the bare minimum required to build a new arch and rooting the commit history from there, and some work with incorporating it into the gitlab CI, containerizing the build and QEMU run, etc... As far as hypervisor status: I'm just about done with incorporating the boot module FDT parsing code, extracting kernel info and ram regions (taken/generalized from arch/arm), plus implementing the arch-specific pieces of domain_create(). On the verge of being able to dive into a guest kernel and see what breaks first :) I'm expected to commit an extra day or two per week in the next month or so at Vates, so this will considerably bump up my cadence in comparison to the last few months. > FYI, I would like to talk more about RISC-V Xen at the Xen Virtual > summit. I'll put it forward as a BoF subject. > > I haven't worked on this, although the RISC-V Hypervisor spec is > progressing towards ratification. > > Alistair > That would be great :) -Bobby
On Mon, 15 Jun 2020, Bobby Eshleman wrote: > On Tue, Jun 16, 2020 at 01:10:17AM +0000, Alistair Francis wrote: > > On Mon, 2020-06-15 at 18:03 -0700, Stefano Stabellini wrote: > > > Any updates? I am looking forward to this :-) > > > > It has been on a slow burn since I became a new dad (shortly after the RFC). > I've gradually regained free time, and so I've been able to change that > slow burn to a moderate burn in the last couple weeks. > > Most of my progress has been around build environment improvements. I've done > some work stripping it down to the bare minimum required to build a new arch > and rooting the commit history from there, and some work with incorporating it > into the gitlab CI, containerizing the build and QEMU run, etc... > > As far as hypervisor status: I'm just about done with incorporating the boot > module FDT parsing code, extracting kernel info and ram regions > (taken/generalized from arch/arm), plus implementing the arch-specific pieces > of domain_create(). > > On the verge of being able to dive into a guest kernel and see what breaks > first :) > > I'm expected to commit an extra day or two per week in the next month or so at > Vates, so this will considerably bump up my cadence in comparison to the last > few months. Great to hear and congratulations! I'll stay tuned. Next time I'll try to rebuild and run your series on QEMU, I might ask you for some help with the setup. > > FYI, I would like to talk more about RISC-V Xen at the Xen Virtual > > summit. I'll put it forward as a BoF subject. > > > > I haven't worked on this, although the RISC-V Hypervisor spec is > > progressing towards ratification. > > > > Alistair > > > > That would be great :) Indeed!
On Tue, Jun 16, 2020 at 01:16:10PM -0700, Stefano Stabellini wrote: > On Mon, 15 Jun 2020, Bobby Eshleman wrote: > > On Tue, Jun 16, 2020 at 01:10:17AM +0000, Alistair Francis wrote: > > > On Mon, 2020-06-15 at 18:03 -0700, Stefano Stabellini wrote: > > > > Any updates? I am looking forward to this :-) > > > > > > > It has been on a slow burn since I became a new dad (shortly after the RFC). > > I've gradually regained free time, and so I've been able to change that > > slow burn to a moderate burn in the last couple weeks. > > > > Most of my progress has been around build environment improvements. I've done > > some work stripping it down to the bare minimum required to build a new arch > > and rooting the commit history from there, and some work with incorporating it > > into the gitlab CI, containerizing the build and QEMU run, etc... > > > > As far as hypervisor status: I'm just about done with incorporating the boot > > module FDT parsing code, extracting kernel info and ram regions > > (taken/generalized from arch/arm), plus implementing the arch-specific pieces > > of domain_create(). > > > > On the verge of being able to dive into a guest kernel and see what breaks > > first :) > > > > I'm expected to commit an extra day or two per week in the next month or so at > > Vates, so this will considerably bump up my cadence in comparison to the last > > few months. > > Great to hear and congratulations! I'll stay tuned. Next time I'll try > to rebuild and run your series on QEMU, I might ask you for some help > with the setup. > Thanks! And absolutely, feel free :)