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[46.204.109.85]) by smtp.gmail.com with ESMTPSA id h10-20020a5d4fca000000b002c3e94cb757sm5269743wrw.117.2023.02.07.06.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 06:46:53 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 435db7ae-a6f6-11ed-933c-83870f6b2ba8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=AMHmfkHHTHE0v8pkna6MESdKkLlHbxr+3nLxEqnuiC4=; b=JJI6HdRHIWyCG0Qcly/fFIST+Tcw6IpEg44w2jU+neU9OLHt6feqdUdJUAC+jR9jMZ 27ARJoCYBkXc0FL0UjJWCPiJEWaASW6ffCQKesJjBg6FvS2WixNHIzBgX38hvF2CAVPU FFJwy7qKs/C+nw8uk0h45KmcB3qZHZGAOvRGEUTTGeOmC1g9oOdfpxHqVNsMl8Kl86wM swKJxCoqZ6zDJPG45WlE59CIdFEeOWAASU0adaTHk40Ey3jyDKp4aruCMpKqGJy2Bp6B aiCHdeIxntwjD6/wnyK2Usu48SNyrjXlylq28uJeyCtaYCgSbHIZPPwFMQlFJtyth0cz wTIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=AMHmfkHHTHE0v8pkna6MESdKkLlHbxr+3nLxEqnuiC4=; b=RTLw/nuySScArWW/Ybk/auOP3rVOhZtEtvbZPXsxTYbJ7D+Kf+Sozd+G6Z1rVYm5R0 mNWRhb8WZBzKhjgUbV05XH+ZlcLbLdaJ8VR4RI+RbVGiso1wcToA5YQD9IUeklWWee4K IQMY22gqGiapw23H2fViNqeqAjaOHTiaefVqx3kRvF3W8MOkDW+FUOwFeCc1UAjcjpMF jtup7StB2LT4EW1PkpmfsjS3B8txJb8m3mCQBpVbA2NaN0nOMVcNP8tKFvXGgDK5enNk pxExPzd/aC+xYa1ISXAv6Spr26HCiuRAu6+j3srdP5IAze2q6J6eyhnIOjyJ6/J66pLh 2Gxw== X-Gm-Message-State: AO0yUKVLLlr+hRd0axTBoCo6GVVEzCfb9UvOHb/nGLYz8I36w36LT+FT x3R5SWN2QQhYuY07YxdoRWGrVC+AlJM= X-Google-Smtp-Source: AK7set98BUQF2JfES/VGC6uCGFzYm12btefrioeDJfWkGepohAAunlIN0GLPqqAWrAY6y6FHTg6uwQ== X-Received: by 2002:adf:e786:0:b0:2c3:def9:7e1a with SMTP id n6-20020adfe786000000b002c3def97e1amr3055414wrm.44.1675781213722; Tue, 07 Feb 2023 06:46:53 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Jan Beulich , Julien Grall , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis , Doug Goldstein Subject: [PATCH v3 00/14] RISCV basic exception handling implementation Date: Tue, 7 Feb 2023 16:46:35 +0200 Message-Id: X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 The patch series is based on another one [Basic early_printk and smoke test implementation] and [introduce generic implementation of macros from bug.h] which haven't been commited yet. The patch series provides a basic implementation of exception handling. It can do only basic things such as decode a cause of an exception, save/restore registers and execute "wfi" instruction if an exception can not be handled. To verify that exception handling works well it was implemented macros from such as BUG/WARN/run_in_exception/assert_failed. The implementation of macros is used "ebreak" instruction and set up bug frame tables for each type of macros. Also it was implemented register save/restore to return and continue work after WARN/run_in_exception. Not all functionality of the macros was implemented as some of them require hard-panic the system which is not available now. Instead of hard-panic 'wfi' instruction is used but it should be definitely changed in the neareset future. It wasn't implemented show_execution_state() and stack trace discovering as it's not necessary now. --- Changes in V3: - Change the name of config RISCV_ISA_RV64IMA to RISCV_ISA_RV64G as instructions from Zicsr and Zifencei extensions aren't part of I extension any more. - Rebase the patch "xen/riscv: introduce an implementation of macros from " on top of patch series [introduce generic implementation of macros from bug.h] - Update commit messages --- Changes in V2: - take the latest riscv_encoding.h from OpenSBI, update it with Xen related changes, and update the commit message with "Origin:" tag and the commit message itself. - add "Origin:" tag to the commit messag of the patch [xen/riscv: add header]. - Remove the patch [xen/riscv: add early_printk_hnum() function] as the functionality provided by the patch isn't used now. - Refactor prcoess.h: move structure offset defines to asm-offsets.c, change register_t to unsigned long. - Refactor entry.S to use offsets defined in asm-offsets.C - Rename {__,}handle_exception to handle_trap() and do_trap() to be more consistent with RISC-V spec. - Merge the pathc which introduces do_unexpected_trap() with the patch [xen/riscv: introduce exception handlers implementation]. - Rename setup_trap_handler() to trap_init() and update correspondingly the patches in the patch series. - Refactor bug.h, remove bug_instr_t type from it. - Refactor decode_trap_cause() function to be more optimization-friendly. - Add two new empty headers: and as they are needed to include which provides ARRAY_SIZE and other macros. - Code style fixes. --- Oleksii Kurochko (14): xen/riscv: change ISA to r64G xen/riscv: add header xen/riscv: add header xen/riscv: introduce empty xen/riscv: introduce empty xen/riscv: introduce exception context xen/riscv: introduce exception handlers implementation xen/riscv: introduce decode_cause() stuff xen/riscv: mask all interrupts xen/riscv: introduce trap_init() xen/riscv: introduce an implementation of macros from xen/riscv: test basic handling stuff automation: modify RISC-V smoke test automation/scripts/qemu-smoke-riscv64.sh | 2 +- xen/arch/riscv/Kconfig | 14 +- xen/arch/riscv/Makefile | 2 + xen/arch/riscv/arch.mk | 2 +- xen/arch/riscv/entry.S | 94 ++ xen/arch/riscv/include/asm/asm.h | 54 ++ xen/arch/riscv/include/asm/bug.h | 38 + xen/arch/riscv/include/asm/cache.h | 6 + xen/arch/riscv/include/asm/csr.h | 84 ++ xen/arch/riscv/include/asm/processor.h | 82 ++ xen/arch/riscv/include/asm/riscv_encoding.h | 927 ++++++++++++++++++++ xen/arch/riscv/include/asm/string.h | 6 + xen/arch/riscv/include/asm/traps.h | 14 + xen/arch/riscv/riscv64/asm-offsets.c | 53 ++ xen/arch/riscv/riscv64/head.S | 5 + xen/arch/riscv/setup.c | 22 +- xen/arch/riscv/traps.c | 233 +++++ xen/arch/riscv/xen.lds.S | 10 + 18 files changed, 1640 insertions(+), 8 deletions(-) create mode 100644 xen/arch/riscv/entry.S create mode 100644 xen/arch/riscv/include/asm/asm.h create mode 100644 xen/arch/riscv/include/asm/bug.h create mode 100644 xen/arch/riscv/include/asm/cache.h create mode 100644 xen/arch/riscv/include/asm/csr.h create mode 100644 xen/arch/riscv/include/asm/processor.h create mode 100644 xen/arch/riscv/include/asm/riscv_encoding.h create mode 100644 xen/arch/riscv/include/asm/string.h create mode 100644 xen/arch/riscv/include/asm/traps.h create mode 100644 xen/arch/riscv/traps.c