[RFC,00/22] vPMU bugfixes and support for PMUv5

Message

Edwin Torok Oct. 25, 2023, 7:29 p.m. UTC

These are a set of patches to improve performance monitoring in Xen.
It starts by fixing MSR_PLATFORM_INFO and making MSR_SMI_COUNT available.
Also allows a pinned Dom0 to read any MSR, there is no reason why this shouldn't be allowed, and it prevents having to recompile Xen in order to investigate a problem that is difficult to reproduce (e.g. one such MSR is the SMI counter).

Then it fixes bugs in each architectural PMU version starting from version 1, and introduces support
for new features up to version 5. This was done by reading the Intel SDM for each version and checking whether Xen implements the needed features correctly.

AMD is next with fixes for performance counters that were readable but not exposed in CPUID, and new support for another performance counter.

There is more to be done here (APERF/MPERF, IBS, temperature monitoring, and I haven't even began approaching uncore counters), but those are difficult to do correctly and I've split them out of this series.

The patches were written in 2021, then git segfaulted when rebasing them and they got lost in a branch until now.
I've rebased and compile-tested them on latest Xen master, but I haven't done any further testing on them yet, hence the RFC prefix to mark these as experimental (e.g. I'm not entirely sure whether some changes got lost in the cpuid.c to cpu-policy.c rebase or not).

I'm sending this out as an RFC so it is not lost again, and I'll resend a proper version once the code has been tested more.
The backport tags attempt to indicate which version of Xen is the oldest one that has a bug fixed by the patch, should a backport be desired.
E.g. Xen with vpmu on would claim it supports PMUv3, but doesn't actually implement it correctly, so those patches+AMD CPUID fix could be backported.

Edwin Török (22):
  x86/msr: MSR_PLATFORM_INFO shouldn't claim that turbo is programmable
  x86/msr: implement MSR_SMI_COUNT for Dom0 on Intel
  x86/msr: always allow a pinned Dom0 to read any unknown MSR
  x86/msr-index: add references to vendor manuals
  x86/PMUv1: report correct information in 0xa CPUID
  x86/PMUv1: limit arch PMCs to 4 for non-Dom0
  x86/PMUv1: allow topdown slots arch perf event
  x86/PMUv1: define macro for max number of events
  x86/PMUv1: consistently use 8 perf counters in Dom0
  x86/PMUv2: limit number of fixed perf counters to 3
  x86/PMUv2: freeze support in IA32_DEBUGCTL
  x86/msr-index: define more architectural MSRs
  x86/vpmu: expose PDCM and IA32_PERF_CAPABILITIES when vpmu is enabled
  x86/msr: RO MSR_TURBO_RATIO_LIMIT{,1,2}, MSR_TEMPERATURE_TARGET
  x86/VPMU: use macros for max supported VPMU version
  x86/PMUv4: support LBR_Frz and CTR_Frz
  x86/PMUv4: IA32_PERF_GLOBAL_{STATUS_SET, INUSE} support
  x86/PMUv4: disable intercept for PERF_GLOBAL_STATUS
  x86/PMUv4: bump max PMU version to 4
  x86/PMUv5: limit available fixed PMCs and enable support
  x86/AMD: fix CPUID for PerfCtr{4,5}
  x86/AMD: add IRPerf support

 xen/arch/x86/cpu-policy.c                   | 32 +++++--
 xen/arch/x86/cpu/vpmu_intel.c               | 99 ++++++++++++++-------
 xen/arch/x86/cpuid.c                        | 40 ++++++++-
 xen/arch/x86/hvm/svm/svm.c                  |  4 +
 xen/arch/x86/hvm/vmx/vmx.c                  | 33 +++++--
 xen/arch/x86/include/asm/msr-index.h        | 79 ++++++++++++++--
 xen/arch/x86/include/asm/vpmu.h             | 32 +++++++
 xen/arch/x86/msr.c                          | 22 +++++
 xen/arch/x86/pv/emul-priv-op.c              | 28 +++---
 xen/include/public/arch-x86/cpufeatureset.h |  6 +-
 xen/include/xen/lib/x86/cpu-policy.h        |  5 +-
 11 files changed, 317 insertions(+), 63 deletions(-)