[v8,0/6] RISC-V runtime detection of extenstions

Message

Oleksii Kurochko Feb. 28, 2025, 8:07 p.m. UTC

Based on riscv,isa property of device tree file parse extenstions which are
available in CPU.

As a part of this feature, drop CONFIG_RISCV_ISA_RV64G and explicitly use
extensions 'i', 'm', 'a', 'zicsr', 'zifencei' as they are necessary for a work
if Xen and it should be true not only for RISC-V 64 (but also for 32 and 128)

---
Changes in v8:
 - Add patch from Andrew which use Zbb to provide arch-optimised bitops
   as in this patch series we made zbb mandatory.
 - Other changes are patch specific please look at specific patch
---

Andrew Cooper (1):
  RISCV/bitops: Use Zbb to provide arch-optimised bitops

Oleksii Kurochko (5):
  xen/README: add compiler and binutils versions for RISCV-64
  automation: drop debian:11-riscv64 container
  xen/riscv: drop CONFIG_RISCV_ISA_RV64G
  xen/riscv: make zbb as mandatory
  xen/riscv: identify specific ISA supported by cpu

 README                                  |   3 +
 automation/gitlab-ci/build.yaml         |  14 -
 automation/scripts/containerize         |   1 -
 xen/arch/riscv/Kconfig                  |  18 -
 xen/arch/riscv/Makefile                 |   1 +
 xen/arch/riscv/arch.mk                  |  13 +-
 xen/arch/riscv/cpufeature.c             | 504 ++++++++++++++++++++++++
 xen/arch/riscv/include/asm/bitops.h     |   7 +
 xen/arch/riscv/include/asm/cmpxchg.h    |  15 +-
 xen/arch/riscv/include/asm/config.h     |   4 +
 xen/arch/riscv/include/asm/cpufeature.h |  59 +++
 xen/arch/riscv/setup.c                  |   3 +
 12 files changed, 588 insertions(+), 54 deletions(-)
 create mode 100644 xen/arch/riscv/cpufeature.c
 create mode 100644 xen/arch/riscv/include/asm/cpufeature.h