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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abf1d1a84b7sm267586566b.19.2025.02.28.12.08.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 12:08:13 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: be87250b-f60f-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740773294; x=1741378094; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zBq3WVBFsdmRZQQQyGw+/2J4204Qtmulox99R0cFeEw=; b=dVt4OEblHrHF2tZIKRuDWeQu5YT6Zqigm5/gGsTYcFxq1kBigDbvcOgFOEDlg/RJ4O MSslL//PG7urnBSE21e38E8o/KRWmsyDh343RaineUgPX9SoqiPaPNJPwgmwzuUkL5qx gs0OYa+YL5V8CpgBHyApPec+iIZcxvpBiCYg/5vnl078T1TFMZLa/yrcvWu1WPM6llVf sDKsVbOGxzi6Lk3xUjUYQd8ryJUQ2rjcY/zBV+BXUr4lvBM36VAGPaOFG6EOoDolTjRo eAsiG9UWuX7rIQjg6rVXYMGhAQESWCQx8L9YJIdsWv00oVscCpfLvLeKHaNp6DryFo3A hALw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773294; x=1741378094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zBq3WVBFsdmRZQQQyGw+/2J4204Qtmulox99R0cFeEw=; b=ZqyMrdw6KXckONeyjksWJOUVbQIdetMrk/2smEamVMUgcBiHNqd+tIHOwwMWd6UWkU AP6sAUz34YWq6Cn2At31wHX4583M17qW1h7Xck6ScrDpsUAEdxrksomOlGyleMf0nw27 0eeaY19QIs6RuusGzULirgNG6yehFfmDkhKcT7aDpw5D0pm8LtMmYdtSw9+/MCR3CiHm wdcHLTzL68MXYXfrTQWNeb504oQXGCws82YOZwr3vM+jNJBKBNNhh0atvKczY02cln/C dD/i2vPVpqajNiyUJhktqTrlYmbyuSLV9K2FZJn/vbgywm6SrHQ3A4zCOYhexKTGWmzt /BuQ== X-Gm-Message-State: AOJu0YzY/w+/G3QF49jm6WWl3FZ+gUM9nS8tqdTdEZdp9544nsamxZxo iXh+8Z4fNI8H9FBXuBZB5tX2vLo8v1X6dbt4x9ISqEpNkHdFYo3W+imIvQ== X-Gm-Gg: ASbGncsjvXF2zNclOa8DbZ5UHVVq8fKtAo3n/o+4xRQLZO386kwhCmlNRJSbUHXG6Th 5K3UMv5aRxMnhUAwnlkdLtd3pw7NqormkDLn1CFhKFZY65T51NckzH2V6emy99Dqck1uLEQqHrE pFMrIZDgoc8IY/4ky2vcFSwyiVJd+MZ0n6V+NF/hKV6HqrZlVpbqn9n9CopKPA8CEjJtHmRWByY UpA89JlwUtTnQ7qN2nG7aYRddjhWzMQv8grJlH4d+pNBozL2CruXqcl14sFTeGMvMRJuOlhRRDZ wsCHC2N1/RjBILPCyUGxzekfwTE= X-Google-Smtp-Source: AGHT+IES8q/iUJm5cNw+qjbCkMoPLxno44J9QsbtU1+OYf8anVgmVMV6PzyGR8nvoGY5cSGSqCiuKQ== X-Received: by 2002:a17:907:3e1e:b0:abc:ca9:45af with SMTP id a640c23a62f3a-abf2642bc2bmr518755366b.18.1740773293957; Fri, 28 Feb 2025 12:08:13 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v8 4/6] xen/riscv: make zbb as mandatory Date: Fri, 28 Feb 2025 21:07:42 +0100 Message-ID: <052daeb00fb90416a30f1deebf42c9b6ca5ff348.1740764258.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: MIME-Version: 1.0 According to riscv/booting.txt, it is expected that Zbb should be supported. Drop ANDN_INSN() in asm/cmpxchg.h as Zbb is mandatory now so `andn` instruction could be used directly. Signed-off-by: Oleksii Kurochko --- Changes in V8: - Drop ANDN_INSN() in asm/cmpxchg.h as Zbb is mandatory now so andn instruction could be used directly. - Update the commit message with the text above. --- Changes in V7: - new patch. --- xen/arch/riscv/arch.mk | 7 ++----- xen/arch/riscv/include/asm/cmpxchg.h | 15 +-------------- 2 files changed, 3 insertions(+), 19 deletions(-) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 3034da76cb..236ea7c8a6 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -9,7 +9,7 @@ riscv-abi-$(CONFIG_RISCV_64) := -mabi=lp64 riscv-march-$(CONFIG_RISCV_64) := rv64 riscv-march-y += ima riscv-march-$(CONFIG_RISCV_ISA_C) += c -riscv-march-y += _zicsr_zifencei +riscv-march-y += _zicsr_zifencei_zbb riscv-generic-flags := $(riscv-abi-y) -march=$(subst $(space),,$(riscv-march-y)) @@ -25,13 +25,10 @@ $(eval $(1) := \ $(call as-insn,$(CC) $(riscv-generic-flags)_$(1),$(value $(1)-insn),_$(1))) endef -zbb-insn := "andn t0$(comma)t0$(comma)t0" -$(call check-extension,zbb) - zihintpause-insn := "pause" $(call check-extension,zihintpause) -extensions := $(zbb) $(zihintpause) +extensions := $(zihintpause) extensions := $(subst $(space),,$(extensions)) diff --git a/xen/arch/riscv/include/asm/cmpxchg.h b/xen/arch/riscv/include/asm/cmpxchg.h index 662d3fd5d4..7d7c89b6fa 100644 --- a/xen/arch/riscv/include/asm/cmpxchg.h +++ b/xen/arch/riscv/include/asm/cmpxchg.h @@ -18,19 +18,6 @@ : "r" (new) \ : "memory" ); -/* - * To not face an issue that gas doesn't understand ANDN instruction - * it is encoded using .insn directive. - */ -#ifdef __riscv_zbb -#define ANDN_INSN(rd, rs1, rs2) \ - ".insn r OP, 0x7, 0x20, " rd ", " rs1 ", " rs2 "\n" -#else -#define ANDN_INSN(rd, rs1, rs2) \ - "not " rd ", " rs2 "\n" \ - "and " rd ", " rs1 ", " rd "\n" -#endif - /* * For LR and SC, the A extension requires that the address held in rs1 be * naturally aligned to the size of the operand (i.e., eight-byte aligned @@ -61,7 +48,7 @@ \ asm volatile ( \ "0: lr.w" lr_sfx " %[old], %[ptr_]\n" \ - ANDN_INSN("%[scratch]", "%[old]", "%[mask]") \ + " andn %[scratch], %[old], %[mask]\n" \ " or %[scratch], %[scratch], %z[new_]\n" \ " sc.w" sc_sfx " %[scratch], %[scratch], %[ptr_]\n" \ " bnez %[scratch], 0b\n" \