From patchwork Tue Dec 22 10:30:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huaitong Han X-Patchwork-Id: 7903611 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 258539F349 for ; Tue, 22 Dec 2015 10:33:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DF68205C2 for ; Tue, 22 Dec 2015 10:33:35 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 35740205BB for ; Tue, 22 Dec 2015 10:33:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aBKDd-0001S9-Fh; Tue, 22 Dec 2015 10:31:01 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aBKDb-0001RO-9O for xen-devel@lists.xen.org; Tue, 22 Dec 2015 10:30:59 +0000 Received: from [193.109.254.147] by server-15.bemta-14.messagelabs.com id 3F/0D-10115-D5629765; Tue, 22 Dec 2015 10:30:53 +0000 X-Env-Sender: huaitong.han@intel.com X-Msg-Ref: server-4.tower-27.messagelabs.com!1450780250!11668560!2 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 31370 invoked from network); 22 Dec 2015 10:30:52 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-4.tower-27.messagelabs.com with SMTP; 22 Dec 2015 10:30:52 -0000 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP; 22 Dec 2015 02:30:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,464,1444719600"; d="scan'208";a="622146908" Received: from huaitong-desk.bj.intel.com ([10.238.135.218]) by FMSMGA003.fm.intel.com with ESMTP; 22 Dec 2015 02:30:49 -0800 From: Huaitong Han To: jbeulich@suse.com, andrew.cooper3@citrix.com, jun.nakajima@intel.com, eddie.dong@intel.com, kevin.tian@intel.com, george.dunlap@eu.citrix.com, ian.jackson@eu.citrix.com, stefano.stabellini@eu.citrix.com, ian.campbell@citrix.com, wei.liu2@citrix.com, keir@xen.org Date: Tue, 22 Dec 2015 18:30:29 +0800 Message-Id: <1450780234-17236-2-git-send-email-huaitong.han@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1450780234-17236-1-git-send-email-huaitong.han@intel.com> References: <1450780234-17236-1-git-send-email-huaitong.han@intel.com> Cc: Huaitong Han , xen-devel@lists.xen.org Subject: [Xen-devel] [PATCH V5 1/6] x86/hvm: pkeys, add the flag to enable Memory Protection Keys X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the flag("pku") to enable Memory Protection Keys, and updates the markdown. Signed-off-by: Huaitong Han Reviewed-by: Andrew Cooper --- docs/misc/xen-command-line.markdown | 10 ++++++++++ xen/arch/x86/cpu/common.c | 10 +++++++++- xen/include/asm-x86/cpufeature.h | 6 +++++- 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown index c103894..36ecf80 100644 --- a/docs/misc/xen-command-line.markdown +++ b/docs/misc/xen-command-line.markdown @@ -1177,6 +1177,16 @@ This option can be specified more than once (up to 8 times at present). ### ple\_window > `= ` +### pku +> `= ` + +> Default: `true` + +Flag to enable Memory Protection Keys. + +The protection-key feature provides an additional mechanism by which IA-32e +paging controls access to usermode addresses. + ### psr (Intel) > `= List of ( cmt: | rmid_max: | cat: | cos_max: | cdp: )` diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 310ec85..a018855 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -22,6 +22,10 @@ boolean_param("xsave", use_xsave); bool_t opt_arat = 1; boolean_param("arat", opt_arat); +/* pku: Flag to enable Memory Protection Keys (default on). */ +static bool_t opt_pku = 1; +boolean_param("pku", opt_pku); + unsigned int opt_cpuid_mask_ecx = ~0u; integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx); unsigned int opt_cpuid_mask_edx = ~0u; @@ -270,7 +274,8 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c) if ( c->cpuid_level >= 0x00000007 ) cpuid_count(0x00000007, 0, &tmp, &c->x86_capability[cpufeat_word(X86_FEATURE_FSGSBASE)], - &tmp, &tmp); + &c->x86_capability[cpufeat_word(X86_FEATURE_PKU)], + &tmp); } /* @@ -323,6 +328,9 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c) if ( cpu_has_xsave ) xstate_init(c); + if ( !opt_pku ) + setup_clear_cpu_cap(X86_FEATURE_PKU); + /* * The vendor-specific functions might have changed features. Now * we do "generic changes." diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index af127cf..ef96514 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -11,7 +11,7 @@ #include -#define NCAPINTS 8 /* N 32-bit words worth of info */ +#define NCAPINTS 9 /* N 32-bit words worth of info */ /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ @@ -163,6 +163,10 @@ #define X86_FEATURE_ADX (7*32+19) /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */ +/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 8 */ +#define X86_FEATURE_PKU (8*32+ 3) /* Protection Keys for Userspace */ +#define X86_FEATURE_OSPKE (8*32+ 4) /* OS Protection Keys Enable */ + #define cpufeat_word(idx) ((idx) / 32) #define cpufeat_bit(idx) ((idx) % 32) #define cpufeat_mask(idx) (_AC(1, U) << cpufeat_bit(idx))