From patchwork Tue Dec 29 11:31:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 7929801 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4B175BEEE5 for ; Tue, 29 Dec 2015 11:36:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6EDFB20221 for ; Tue, 29 Dec 2015 11:36:33 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 775D8201EC for ; Tue, 29 Dec 2015 11:36:32 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aDsVq-0001K9-8X; Tue, 29 Dec 2015 11:32:22 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aDsVp-0001JX-6O for xen-devel@lists.xen.org; Tue, 29 Dec 2015 11:32:21 +0000 Received: from [85.158.139.211] by server-2.bemta-5.messagelabs.com id 17/5B-31450-44F62865; Tue, 29 Dec 2015 11:32:20 +0000 X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-12.tower-206.messagelabs.com!1451388738!13110550!1 X-Originating-IP: [192.55.52.120] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 64273 invoked from network); 29 Dec 2015 11:32:19 -0000 Received: from mga04.intel.com (HELO mga04.intel.com) (192.55.52.120) by server-12.tower-206.messagelabs.com with SMTP; 29 Dec 2015 11:32:19 -0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP; 29 Dec 2015 03:32:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,495,1444719600"; d="scan'208";a="880368153" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.13.40]) by orsmga002.jf.intel.com with ESMTP; 29 Dec 2015 03:32:15 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Tue, 29 Dec 2015 19:31:48 +0800 Message-Id: <1451388711-18646-2-git-send-email-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.4.8 In-Reply-To: <1451388711-18646-1-git-send-email-haozhong.zhang@intel.com> References: <1451388711-18646-1-git-send-email-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Kevin Tian , Keir Fraser , Ian Campbell , Stefano Stabellini , Jun Nakajima , Andrew Cooper , Ian Jackson , Jan Beulich , Wei Liu Subject: [Xen-devel] [PATCH 1/4] x86/hvm: allow guest to use clflushopt and clwb X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Pass CPU features CLFLUSHOPT and CLWB into HVM domain so that those two instructions can be used by guest. The specification of above two instructions can be found in https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Haozhong Zhang --- tools/libxc/xc_cpufeature.h | 3 ++- tools/libxc/xc_cpuid_x86.c | 4 +++- xen/arch/x86/hvm/hvm.c | 7 +++++++ xen/include/asm-x86/cpufeature.h | 5 +++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h index c3ddc80..5288ac6 100644 --- a/tools/libxc/xc_cpufeature.h +++ b/tools/libxc/xc_cpufeature.h @@ -140,6 +140,7 @@ #define X86_FEATURE_RDSEED 18 /* RDSEED instruction */ #define X86_FEATURE_ADX 19 /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP 20 /* Supervisor Mode Access Protection */ - +#define X86_FEATURE_CLFLUSHOPT 23 /* CLFLUSHOPT instruction */ +#define X86_FEATURE_CLWB 24 /* CLWB instruction */ #endif /* __LIBXC_CPUFEATURE_H */ diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c index 8882c01..fecfd6c 100644 --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -426,7 +426,9 @@ static void xc_cpuid_hvm_policy(xc_interface *xch, bitmaskof(X86_FEATURE_RDSEED) | bitmaskof(X86_FEATURE_ADX) | bitmaskof(X86_FEATURE_SMAP) | - bitmaskof(X86_FEATURE_FSGSBASE)); + bitmaskof(X86_FEATURE_FSGSBASE) | + bitmaskof(X86_FEATURE_CLWB) | + bitmaskof(X86_FEATURE_CLFLUSHOPT)); } else regs[1] = 0; regs[0] = regs[2] = regs[3] = 0; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 21470ec..58c83a5 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4598,6 +4598,13 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, /* Don't expose INVPCID to non-hap hvm. */ if ( (count == 0) && !hap_enabled(d) ) *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); + + if ( (count == 0) && !cpu_has_clflushopt ) + *ebx &= ~cpufeat_mask(X86_FEATURE_CLFLUSHOPT); + + if ( (count == 0) && !cpu_has_clwb ) + *ebx &= ~cpufeat_mask(X86_FEATURE_CLWB); + break; case 0xb: /* Fix the x2APIC identifier. */ diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index ef96514..5818228 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -162,6 +162,8 @@ #define X86_FEATURE_RDSEED (7*32+18) /* RDSEED instruction */ #define X86_FEATURE_ADX (7*32+19) /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */ +#define X86_FEATURE_CLFLUSHOPT (7*32+23) /* CLFLUSHOPT instruction */ +#define X86_FEATURE_CLWB (7*32+24) /* CLWB instruction */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 8 */ #define X86_FEATURE_PKU (8*32+ 3) /* Protection Keys for Userspace */ @@ -234,6 +236,9 @@ #define cpu_has_xgetbv1 boot_cpu_has(X86_FEATURE_XGETBV1) #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) +#define cpu_has_clflushopt boot_cpu_has(X86_FEATURE_CLFLUSHOPT) +#define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB) + enum _cache_type { CACHE_TYPE_NULL = 0, CACHE_TYPE_DATA = 1,