From patchwork Tue Dec 29 11:31:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 7929771 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2C971BEEED for ; Tue, 29 Dec 2015 11:35:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 197CE20221 for ; Tue, 29 Dec 2015 11:35:02 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D849B2015A for ; Tue, 29 Dec 2015 11:35:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aDsVs-0001LM-Oa; Tue, 29 Dec 2015 11:32:24 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aDsVr-0001Kn-B0 for xen-devel@lists.xen.org; Tue, 29 Dec 2015 11:32:23 +0000 Received: from [85.158.143.35] by server-3.bemta-4.messagelabs.com id 88/FD-31122-64F62865; Tue, 29 Dec 2015 11:32:22 +0000 X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-3.tower-21.messagelabs.com!1451388735!7138989!2 X-Originating-IP: [134.134.136.24] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjQgPT4gMzkwOTcx\n X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 38741 invoked from network); 29 Dec 2015 11:32:21 -0000 Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by server-3.tower-21.messagelabs.com with SMTP; 29 Dec 2015 11:32:21 -0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 29 Dec 2015 03:32:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,495,1444719600"; d="scan'208";a="20651443" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.13.40]) by fmsmga004.fm.intel.com with ESMTP; 29 Dec 2015 03:32:18 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Tue, 29 Dec 2015 19:31:49 +0800 Message-Id: <1451388711-18646-3-git-send-email-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.4.8 In-Reply-To: <1451388711-18646-1-git-send-email-haozhong.zhang@intel.com> References: <1451388711-18646-1-git-send-email-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Kevin Tian , Keir Fraser , Ian Campbell , Stefano Stabellini , Jun Nakajima , Andrew Cooper , Ian Jackson , Jan Beulich , Wei Liu Subject: [Xen-devel] [PATCH 2/4] x86/hvm: add support for pcommit instruction X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Pass PCOMMIT CPU feature into HMV domain. Currently, we do not intercept pcommit instruction for L1 guest, and allow L1 to intercept pcommit instruction for L2 guest. The specification of pcommit instruction can be found in https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Haozhong Zhang --- tools/libxc/xc_cpufeature.h | 1 + tools/libxc/xc_cpuid_x86.c | 1 + xen/arch/x86/hvm/hvm.c | 3 +++ xen/arch/x86/hvm/vmx/vmcs.c | 6 +++++- xen/arch/x86/hvm/vmx/vmx.c | 1 + xen/arch/x86/hvm/vmx/vvmx.c | 3 +++ xen/include/asm-x86/cpufeature.h | 2 ++ xen/include/asm-x86/hvm/vmx/vmcs.h | 3 +++ xen/include/asm-x86/hvm/vmx/vmx.h | 1 + 9 files changed, 20 insertions(+), 1 deletion(-) diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h index 5288ac6..ee53679 100644 --- a/tools/libxc/xc_cpufeature.h +++ b/tools/libxc/xc_cpufeature.h @@ -140,6 +140,7 @@ #define X86_FEATURE_RDSEED 18 /* RDSEED instruction */ #define X86_FEATURE_ADX 19 /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP 20 /* Supervisor Mode Access Protection */ +#define X86_FEATURE_PCOMMIT 22 /* PCOMMIT instruction */ #define X86_FEATURE_CLFLUSHOPT 23 /* CLFLUSHOPT instruction */ #define X86_FEATURE_CLWB 24 /* CLWB instruction */ diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c index fecfd6c..c142595 100644 --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -427,6 +427,7 @@ static void xc_cpuid_hvm_policy(xc_interface *xch, bitmaskof(X86_FEATURE_ADX) | bitmaskof(X86_FEATURE_SMAP) | bitmaskof(X86_FEATURE_FSGSBASE) | + bitmaskof(X86_FEATURE_PCOMMIT) | bitmaskof(X86_FEATURE_CLWB) | bitmaskof(X86_FEATURE_CLFLUSHOPT)); } else diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 58c83a5..d12f619 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4605,6 +4605,9 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, if ( (count == 0) && !cpu_has_clwb ) *ebx &= ~cpufeat_mask(X86_FEATURE_CLWB); + if ( (count == 0) && !cpu_has_pcommit ) + *ebx &= ~cpufeat_mask(X86_FEATURE_PCOMMIT); + break; case 0xb: /* Fix the x2APIC identifier. */ diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index edd4c8d..9092a98 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -242,7 +242,8 @@ static int vmx_init_vmcs_config(void) SECONDARY_EXEC_ENABLE_INVPCID | SECONDARY_EXEC_ENABLE_VM_FUNCTIONS | SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS | - SECONDARY_EXEC_XSAVES); + SECONDARY_EXEC_XSAVES | + SECONDARY_EXEC_PCOMMIT); rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap); if ( _vmx_misc_cap & VMX_MISC_VMWRITE_ALL ) opt |= SECONDARY_EXEC_ENABLE_VMCS_SHADOWING; @@ -1075,6 +1076,9 @@ static int construct_vmcs(struct vcpu *v) __vmwrite(PLE_WINDOW, ple_window); } + if ( cpu_has_vmx_pcommit ) + v->arch.hvm_vmx.secondary_exec_control &= ~SECONDARY_EXEC_PCOMMIT; + if ( cpu_has_vmx_secondary_exec_control ) __vmwrite(SECONDARY_VM_EXEC_CONTROL, v->arch.hvm_vmx.secondary_exec_control); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index b918b8a..0991cdf 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3517,6 +3517,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) case EXIT_REASON_ACCESS_LDTR_OR_TR: case EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED: case EXIT_REASON_INVPCID: + case EXIT_REASON_PCOMMIT: /* fall through */ default: exit_and_crash: diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index ea1052e..271ec70 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1950,6 +1950,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) SECONDARY_EXEC_ENABLE_VPID | SECONDARY_EXEC_UNRESTRICTED_GUEST | SECONDARY_EXEC_ENABLE_EPT; + if ( cpu_has_vmx_pcommit ) + data |= SECONDARY_EXEC_PCOMMIT; data = gen_vmx_msr(data, 0, host_data); break; case MSR_IA32_VMX_EXIT_CTLS: @@ -2226,6 +2228,7 @@ int nvmx_n2_vmexit_handler(struct cpu_user_regs *regs, case EXIT_REASON_VMXON: case EXIT_REASON_INVEPT: case EXIT_REASON_XSETBV: + case EXIT_REASON_PCOMMIT: /* inject to L1 */ nvcpu->nv_vmexit_pending = 1; break; diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 5818228..7491e37 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -162,6 +162,7 @@ #define X86_FEATURE_RDSEED (7*32+18) /* RDSEED instruction */ #define X86_FEATURE_ADX (7*32+19) /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */ +#define X86_FEATURE_PCOMMIT (7*32+22) /* PCOMMIT instruction */ #define X86_FEATURE_CLFLUSHOPT (7*32+23) /* CLFLUSHOPT instruction */ #define X86_FEATURE_CLWB (7*32+24) /* CLWB instruction */ @@ -238,6 +239,7 @@ #define cpu_has_clflushopt boot_cpu_has(X86_FEATURE_CLFLUSHOPT) #define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB) +#define cpu_has_pcommit boot_cpu_has(X86_FEATURE_PCOMMIT) enum _cache_type { CACHE_TYPE_NULL = 0, diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h index d1496b8..77cf8da 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -236,6 +236,7 @@ extern u32 vmx_vmentry_control; #define SECONDARY_EXEC_ENABLE_PML 0x00020000 #define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 #define SECONDARY_EXEC_XSAVES 0x00100000 +#define SECONDARY_EXEC_PCOMMIT 0x00200000 extern u32 vmx_secondary_exec_control; #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 @@ -303,6 +304,8 @@ extern u64 vmx_ept_vpid_cap; (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_PML) #define cpu_has_vmx_xsaves \ (vmx_secondary_exec_control & SECONDARY_EXEC_XSAVES) +#define cpu_has_vmx_pcommit \ + (vmx_secondary_exec_control & SECONDARY_EXEC_PCOMMIT) #define VMCS_RID_TYPE_MASK 0x80000000 diff --git a/xen/include/asm-x86/hvm/vmx/vmx.h b/xen/include/asm-x86/hvm/vmx/vmx.h index 1719965..14f3d32 100644 --- a/xen/include/asm-x86/hvm/vmx/vmx.h +++ b/xen/include/asm-x86/hvm/vmx/vmx.h @@ -213,6 +213,7 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) #define EXIT_REASON_PML_FULL 62 #define EXIT_REASON_XSAVES 63 #define EXIT_REASON_XRSTORS 64 +#define EXIT_REASON_PCOMMIT 65 /* * Interruption-information format