From patchwork Thu Dec 31 03:03:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 7935311 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A8B7F9F32E for ; Thu, 31 Dec 2015 03:07:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A13C320219 for ; Thu, 31 Dec 2015 03:07:28 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B75E6201BB for ; Thu, 31 Dec 2015 03:07:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aETXm-0000OE-FL; Thu, 31 Dec 2015 03:04:50 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aETXl-0000Ne-BJ for xen-devel@lists.xen.org; Thu, 31 Dec 2015 03:04:49 +0000 Received: from [85.158.137.68] by server-11.bemta-3.messagelabs.com id 6C/7F-32641-05B94865; Thu, 31 Dec 2015 03:04:48 +0000 X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-7.tower-31.messagelabs.com!1451531085!5843005!1 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 54165 invoked from network); 31 Dec 2015 03:04:45 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-7.tower-31.messagelabs.com with SMTP; 31 Dec 2015 03:04:45 -0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 30 Dec 2015 19:04:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,503,1444719600"; d="scan'208";a="851077302" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.13.40]) by orsmga001.jf.intel.com with ESMTP; 30 Dec 2015 19:04:41 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org, Jan Beulich , Boris Ostrovsky , Kevin Tian Date: Thu, 31 Dec 2015 11:03:33 +0800 Message-Id: <1451531020-29964-7-git-send-email-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.4.8 In-Reply-To: <1451531020-29964-1-git-send-email-haozhong.zhang@intel.com> References: <1451531020-29964-1-git-send-email-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Keir Fraser , Suravee Suthikulpanit , Andrew Cooper , Aravind Gopalakrishnan , Jun Nakajima Subject: [Xen-devel] [PATCH v3 06/13] x86/hvm: Collect information of TSC scaling ratio X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Both VMX TSC scaling and SVM TSC ratio use the 64-bit TSC scaling ratio, but the number of fractional bits of the ratio is different between VMX and SVM. This patch adds the architecture code to collect the number of fractional bits and other related information into fields of struct hvm_function_table so that they can be used in the common code. Signed-off-by: Haozhong Zhang Reviewed-by: Kevin Tian Reviewed-by: Boris Ostrovsky --- Changes in v3: (addressing Kevin Tian's comments) * Fix a typo: maxmimum -> maximum xen/arch/x86/hvm/svm/svm.c | 7 +++++++ xen/include/asm-x86/hvm/hvm.h | 12 ++++++++++++ 2 files changed, 19 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 8891c78..95795ce 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1451,6 +1451,9 @@ const struct hvm_function_table * __init start_svm(void) if ( !cpu_has_svm_nrips ) clear_bit(SVM_FEATURE_DECODEASSISTS, &svm_feature_flags); + if ( cpu_has_tsc_ratio ) + svm_function_table.tsc_scaling_supported = 1; + #define P(p,s) if ( p ) { printk(" - %s\n", s); printed = 1; } P(cpu_has_svm_npt, "Nested Page Tables (NPT)"); P(cpu_has_svm_lbrv, "Last Branch Record (LBR) Virtualisation"); @@ -2272,6 +2275,10 @@ static struct hvm_function_table __initdata svm_function_table = { .nhvm_hap_walk_L1_p2m = nsvm_hap_walk_L1_p2m, .scale_tsc = svm_scale_tsc, + + .default_tsc_scaling_ratio = DEFAULT_TSC_RATIO, + .max_tsc_scaling_ratio = ~TSC_RATIO_RSVD_BITS, + .tsc_scaling_ratio_frac_bits = 32, }; void svm_vmexit_handler(struct cpu_user_regs *regs) diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h index ba6259e..12f9f24 100644 --- a/xen/include/asm-x86/hvm/hvm.h +++ b/xen/include/asm-x86/hvm/hvm.h @@ -100,6 +100,18 @@ struct hvm_function_table { unsigned int hap_capabilities; /* + * Parameters of hardware-assisted TSC scaling. + */ + /* is TSC scaling supported? */ + bool_t tsc_scaling_supported; + /* number of bits of the fractional part of TSC scaling ratio */ + uint8_t tsc_scaling_ratio_frac_bits; + /* default TSC scaling ratio (no scaling) */ + uint64_t default_tsc_scaling_ratio; + /* maximum-allowed TSC scaling ratio */ + uint64_t max_tsc_scaling_ratio; + + /* * Initialise/destroy HVM domain/vcpu resources */ int (*domain_initialise)(struct domain *d);