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DIR:OUT; SFP:1102; SCL:1; SRVR:BY5PR18MB3363; H:BY5PR18MB3394.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: suse.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: zX6k+GPFXBL6AD47yqLjZUYqXheq84vklg41oUIw119pHywE8vvSODs1Fzd2oGG3qStb6xDfldEg/pLxdrTm/BDSfndpVMkuUAvqgVZihsyW3wi5Tn/TbMXwu0+6c2sJnjY8nIG4zoE/t2YkUMldfdrJ8osKQW76M4AP4tYspAcDTbdVDZ5g0Qu1jeEO/gleF+9liYgshxQQ8OH08N3uNwWcwheoTdqC26vkN2QAb0NomLwbayRfskUOO4e88FBZBrb4YPYLTrJ1KWfsogR7KN7mYBR/P8IZjSeuBiiM6U5QcsoS90bk1Fv4Q2InHkV3EcirophH04zxiJKyHm8XAwd1EPGJYZ0p290NB0C39rpOBRqksFXaTlzXvlDTUsJYuLcggxJhxJfUJdArcUP5AMCgbvHHU9//CXpsj+5iFEA= Content-ID: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 56f1dc08-63a3-4956-15c9-08d6fe164f86 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Jul 2019 11:21:49.8805 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 856b813c-16e5-49a5-85ec-6f081e13b527 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JBeulich@suse.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR18MB3363 X-OriginatorOrg: suse.com Subject: [Xen-devel] [PATCH v9 10/23] x86emul: complete support of AVX512_VBMI insns X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , RogerPau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Also add testing of ones support for which was added before. Sadly gcc's command line option naming is not in line with Intel's naming of the feature, which makes it necessary to mis-name things in the test harness. Since the only new insn here and in particular its memory access pattern follows the usual scheme, I didn't think it was necessary to add a contrived test specifically for it, beyond the Disp8 scaling one. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- v6: New. --- a/tools/tests/x86_emulator/Makefile +++ b/tools/tests/x86_emulator/Makefile @@ -16,7 +16,7 @@ vpath %.c $(XEN_ROOT)/xen/lib/x86 CFLAGS += $(CFLAGS_xeninclude) -SIMD := 3dnow sse sse2 sse4 avx avx2 xop avx512f avx512bw avx512dq avx512er +SIMD := 3dnow sse sse2 sse4 avx avx2 xop avx512f avx512bw avx512dq avx512er avx512vbmi FMA := fma4 fma SG := avx2-sg avx512f-sg avx512vl-sg TESTCASES := blowfish $(SIMD) $(FMA) $(SG) @@ -83,6 +83,9 @@ avx512dq-flts := $(avx512f-flts) avx512er-vecs := 64 avx512er-ints := avx512er-flts := 4 8 +avx512vbmi-vecs := $(avx512bw-vecs) +avx512vbmi-ints := $(avx512bw-ints) +avx512vbmi-flts := $(avx512bw-flts) avx512f-opmask-vecs := 2 avx512dq-opmask-vecs := 1 2 --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -542,6 +542,7 @@ static const struct test avx512_vbmi_all INSN(permb, 66, 0f38, 8d, vl, b, vl), INSN(permi2b, 66, 0f38, 75, vl, b, vl), INSN(permt2b, 66, 0f38, 7d, vl, b, vl), + INSN(pmultishiftqb, 66, 0f38, 83, vl, q, vl), }; static const struct test avx512_vbmi2_all[] = { --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -27,6 +27,7 @@ asm ( ".pushsection .test, \"ax\", @prog #include "avx512bw.h" #include "avx512dq.h" #include "avx512er.h" +#include "avx512vbmi.h" #define verbose false /* Switch to true for far more logging. */ @@ -127,6 +128,16 @@ static bool simd_check_avx512bw_vl(void) return cpu_has_avx512bw && cpu_has_avx512vl; } +static bool simd_check_avx512vbmi(void) +{ + return cpu_has_avx512_vbmi; +} + +static bool simd_check_avx512vbmi_vl(void) +{ + return cpu_has_avx512_vbmi && cpu_has_avx512vl; +} + static void simd_set_regs(struct cpu_user_regs *regs) { if ( cpu_has_mmx ) @@ -372,6 +383,18 @@ static const struct { SIMD(AVX512ER f32x16, avx512er, 64f4), SIMD(AVX512ER f64 scalar,avx512er, f8), SIMD(AVX512ER f64x8, avx512er, 64f8), + SIMD(AVX512_VBMI s8x64, avx512vbmi, 64i1), + SIMD(AVX512_VBMI u8x64, avx512vbmi, 64u1), + SIMD(AVX512_VBMI s16x32, avx512vbmi, 64i2), + SIMD(AVX512_VBMI u16x32, avx512vbmi, 64u2), + AVX512VL(_VBMI+VL s8x16, avx512vbmi, 16i1), + AVX512VL(_VBMI+VL u8x16, avx512vbmi, 16u1), + AVX512VL(_VBMI+VL s8x32, avx512vbmi, 32i1), + AVX512VL(_VBMI+VL u8x32, avx512vbmi, 32u1), + AVX512VL(_VBMI+VL s16x8, avx512vbmi, 16i2), + AVX512VL(_VBMI+VL u16x8, avx512vbmi, 16u2), + AVX512VL(_VBMI+VL s16x16, avx512vbmi, 32i2), + AVX512VL(_VBMI+VL u16x16, avx512vbmi, 32u2), #undef AVX512VL_ #undef AVX512VL #undef SIMD_ --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -493,6 +493,7 @@ static const struct ext0f38_table { [0x7a ... 0x7c] = { .simd_size = simd_none, .two_op = 1 }, [0x7d ... 0x7e] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, [0x7f] = { .simd_size = simd_packed_fp, .d8s = d8s_vl }, + [0x83] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, [0x88] = { .simd_size = simd_packed_fp, .two_op = 1, .d8s = d8s_dq }, [0x89] = { .simd_size = simd_packed_int, .two_op = 1, .d8s = d8s_dq }, [0x8a] = { .simd_size = simd_packed_fp, .to_mem = 1, .two_op = 1, .d8s = d8s_dq }, @@ -8999,6 +9000,12 @@ x86_emulate( ASSERT(!state->simd_size); break; + case X86EMUL_OPC_EVEX_66(0x0f38, 0x83): /* vpmultishiftqb [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + generate_exception_if(!evex.w, EXC_UD); + host_and_vcpu_must_have(avx512_vbmi); + fault_suppression = false; + goto avx512f_no_sae; + case X86EMUL_OPC_VEX_66(0x0f38, 0x8c): /* vpmaskmov{d,q} mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x8e): /* vpmaskmov{d,q} {x,y}mm,{x,y}mm,mem */ generate_exception_if(ea.type != OP_MEM, EXC_UD);