From patchwork Sun Jan 17 21:58:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 8051071 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7B82C9F818 for ; Sun, 17 Jan 2016 22:04:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A8863205D8 for ; Sun, 17 Jan 2016 22:04:38 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B0059205EF for ; Sun, 17 Jan 2016 22:03:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aKvNF-0003Vx-3l; Sun, 17 Jan 2016 22:00:37 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aKvND-0003UT-HB for xen-devel@lists.xen.org; Sun, 17 Jan 2016 22:00:35 +0000 Received: from [85.158.143.35] by server-2.bemta-4.messagelabs.com id D5/A9-08977-20F0C965; Sun, 17 Jan 2016 22:00:34 +0000 X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-10.tower-21.messagelabs.com!1453068033!10567035!1 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 21733 invoked from network); 17 Jan 2016 22:00:33 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-10.tower-21.messagelabs.com with SMTP; 17 Jan 2016 22:00:33 -0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 17 Jan 2016 14:00:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,309,1449561600"; d="scan'208";a="862676926" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.13.26]) by orsmga001.jf.intel.com with ESMTP; 17 Jan 2016 14:00:31 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org, Jan Beulich , Boris Ostrovsky , Kevin Tian Date: Mon, 18 Jan 2016 05:58:58 +0800 Message-Id: <1453067939-9121-10-git-send-email-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.4.8 In-Reply-To: <1453067939-9121-1-git-send-email-haozhong.zhang@intel.com> References: <1453067939-9121-1-git-send-email-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Keir Fraser , Suravee Suthikulpanit , Andrew Cooper , Aravind Gopalakrishnan , Jun Nakajima Subject: [Xen-devel] [PATCH v4 09/10] vmx: Add VMX RDTSC(P) scaling support X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the initialization and setup code for VMX TSC scaling. Signed-off-by: Haozhong Zhang Acked-by: Kevin Tian --- Changes in v4: (addressing Jan Beulich's comments) * Set TSC scaling parameters in hvm_funcs conditionally. xen/arch/x86/hvm/hvm.c | 3 +++ xen/arch/x86/hvm/vmx/vmcs.c | 12 +++++++++--- xen/arch/x86/hvm/vmx/vmx.c | 20 ++++++++++++++++++++ xen/include/asm-x86/hvm/hvm.h | 3 +++ xen/include/asm-x86/hvm/vmx/vmcs.h | 7 +++++++ 5 files changed, 42 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index ddc60a7..2469a5e 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -338,6 +338,9 @@ void hvm_setup_tsc_scaling(struct vcpu *v) { v->arch.hvm_vcpu.tsc_scaling_ratio = hvm_get_tsc_scaling_ratio(v->domain->arch.tsc_khz); + + if ( hvm_funcs.setup_tsc_scaling ) + hvm_funcs.setup_tsc_scaling(v); } void hvm_set_guest_tsc_fixed(struct vcpu *v, u64 guest_tsc, u64 at_tsc) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index edd4c8d..8f16c3a 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -149,6 +149,7 @@ static void __init vmx_display_features(void) P(cpu_has_vmx_vmfunc, "VM Functions"); P(cpu_has_vmx_virt_exceptions, "Virtualisation Exceptions"); P(cpu_has_vmx_pml, "Page Modification Logging"); + P(cpu_has_vmx_tsc_scaling, "TSC Scaling"); #undef P if ( !printed ) @@ -242,7 +243,8 @@ static int vmx_init_vmcs_config(void) SECONDARY_EXEC_ENABLE_INVPCID | SECONDARY_EXEC_ENABLE_VM_FUNCTIONS | SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS | - SECONDARY_EXEC_XSAVES); + SECONDARY_EXEC_XSAVES | + SECONDARY_EXEC_TSC_SCALING); rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap); if ( _vmx_misc_cap & VMX_MISC_VMWRITE_ALL ) opt |= SECONDARY_EXEC_ENABLE_VMCS_SHADOWING; @@ -999,7 +1001,7 @@ static int construct_vmcs(struct vcpu *v) __vmwrite(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_control); v->arch.hvm_vmx.exec_control = vmx_cpu_based_exec_control; - if ( d->arch.vtsc ) + if ( d->arch.vtsc && !cpu_has_vmx_tsc_scaling ) v->arch.hvm_vmx.exec_control |= CPU_BASED_RDTSC_EXITING; v->arch.hvm_vmx.secondary_exec_control = vmx_secondary_exec_control; @@ -1281,6 +1283,9 @@ static int construct_vmcs(struct vcpu *v) if ( cpu_has_vmx_xsaves ) __vmwrite(XSS_EXIT_BITMAP, 0); + if ( cpu_has_vmx_tsc_scaling ) + __vmwrite(TSC_MULTIPLIER, v->arch.hvm_vcpu.tsc_scaling_ratio); + vmx_vmcs_exit(v); /* PVH: paging mode is updated by arch_set_info_guest(). */ @@ -1863,7 +1868,8 @@ void vmcs_dump_vcpu(struct vcpu *v) vmr32(VM_EXIT_REASON), vmr(EXIT_QUALIFICATION)); printk("IDTVectoring: info=%08x errcode=%08x\n", vmr32(IDT_VECTORING_INFO), vmr32(IDT_VECTORING_ERROR_CODE)); - printk("TSC Offset = 0x%016lx\n", vmr(TSC_OFFSET)); + printk("TSC Offset = 0x%016lx TSC Multiplier = 0x%016lx\n", + vmr(TSC_OFFSET), vmr(TSC_MULTIPLIER)); if ( (v->arch.hvm_vmx.exec_control & CPU_BASED_TPR_SHADOW) || (vmx_pin_based_exec_control & PIN_BASED_POSTED_INTERRUPT) ) printk("TPR Threshold = 0x%02x PostedIntrVec = 0x%02x\n", diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 6285689..fa12782 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -115,6 +115,7 @@ static int vmx_vcpu_initialise(struct vcpu *v) v->arch.schedule_tail = vmx_do_resume; v->arch.ctxt_switch_from = vmx_ctxt_switch_from; v->arch.ctxt_switch_to = vmx_ctxt_switch_to; + v->arch.hvm_vcpu.tsc_scaling_ratio = VMX_TSC_MULTIPLIER_DEFAULT; if ( (rc = vmx_create_vmcs(v)) != 0 ) { @@ -1105,6 +1106,13 @@ static void vmx_handle_cd(struct vcpu *v, unsigned long value) } } +static void vmx_setup_tsc_scaling(struct vcpu *v) +{ + vmx_vmcs_enter(v); + __vmwrite(TSC_MULTIPLIER, v->arch.hvm_vcpu.tsc_scaling_ratio); + vmx_vmcs_exit(v); +} + static void vmx_set_tsc_offset(struct vcpu *v, u64 offset, u64 at_tsc) { vmx_vmcs_enter(v); @@ -2003,6 +2011,10 @@ static struct hvm_function_table __initdata vmx_function_table = { .altp2m_vcpu_update_vmfunc_ve = vmx_vcpu_update_vmfunc_ve, .altp2m_vcpu_emulate_ve = vmx_vcpu_emulate_ve, .altp2m_vcpu_emulate_vmfunc = vmx_vcpu_emulate_vmfunc, + .default_tsc_scaling_ratio = VMX_TSC_MULTIPLIER_DEFAULT, + .max_tsc_scaling_ratio = VMX_TSC_MULTIPLIER_MAX, + .tsc_scaling_ratio_frac_bits = 48, + .setup_tsc_scaling = vmx_setup_tsc_scaling, }; /* Handle VT-d posted-interrupt when VCPU is running. */ @@ -2107,6 +2119,14 @@ const struct hvm_function_table * __init start_vmx(void) && cpu_has_vmx_secondary_exec_control ) vmx_function_table.pvh_supported = 1; + if ( cpu_has_vmx_tsc_scaling ) + { + vmx_function_table.default_tsc_scaling_ratio = VMX_TSC_MULTIPLIER_DEFAULT; + vmx_function_table.max_tsc_scaling_ratio = VMX_TSC_MULTIPLIER_MAX; + vmx_function_table.tsc_scaling_ratio_frac_bits = 48; + vmx_function_table.setup_tsc_scaling = vmx_setup_tsc_scaling; + } + setup_vmcs_dump(); return &vmx_function_table; diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h index 5588b92..10b9457 100644 --- a/xen/include/asm-x86/hvm/hvm.h +++ b/xen/include/asm-x86/hvm/hvm.h @@ -223,6 +223,9 @@ struct hvm_function_table { void (*altp2m_vcpu_update_vmfunc_ve)(struct vcpu *v); bool_t (*altp2m_vcpu_emulate_ve)(struct vcpu *v); int (*altp2m_vcpu_emulate_vmfunc)(struct cpu_user_regs *regs); + + /* Architecture function to setup TSC scaling ratio */ + void (*setup_tsc_scaling)(struct vcpu *v); }; extern struct hvm_function_table hvm_funcs; diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h index d1496b8..fdece44 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -236,6 +236,7 @@ extern u32 vmx_vmentry_control; #define SECONDARY_EXEC_ENABLE_PML 0x00020000 #define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 #define SECONDARY_EXEC_XSAVES 0x00100000 +#define SECONDARY_EXEC_TSC_SCALING 0x02000000 extern u32 vmx_secondary_exec_control; #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 @@ -258,6 +259,9 @@ extern u64 vmx_ept_vpid_cap; #define VMX_MISC_CR3_TARGET 0x01ff0000 #define VMX_MISC_VMWRITE_ALL 0x20000000 +#define VMX_TSC_MULTIPLIER_DEFAULT 0x0001000000000000ULL +#define VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL + #define cpu_has_wbinvd_exiting \ (vmx_secondary_exec_control & SECONDARY_EXEC_WBINVD_EXITING) #define cpu_has_vmx_virtualize_apic_accesses \ @@ -303,6 +307,8 @@ extern u64 vmx_ept_vpid_cap; (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_PML) #define cpu_has_vmx_xsaves \ (vmx_secondary_exec_control & SECONDARY_EXEC_XSAVES) +#define cpu_has_vmx_tsc_scaling \ + (vmx_secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) #define VMCS_RID_TYPE_MASK 0x80000000 @@ -378,6 +384,7 @@ enum vmcs_field { VMWRITE_BITMAP = 0x00002028, VIRT_EXCEPTION_INFO = 0x0000202a, XSS_EXIT_BITMAP = 0x0000202c, + TSC_MULTIPLIER = 0x00002032, GUEST_PHYSICAL_ADDRESS = 0x00002400, VMCS_LINK_POINTER = 0x00002800, GUEST_IA32_DEBUGCTL = 0x00002802,