From patchwork Thu Feb 4 07:00:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huaitong Han X-Patchwork-Id: 8214121 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 121289F37A for ; Thu, 4 Feb 2016 07:03:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 14E3620357 for ; Thu, 4 Feb 2016 07:02:59 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1125B202F8 for ; Thu, 4 Feb 2016 07:02:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aRDu5-00012B-LQ; Thu, 04 Feb 2016 07:00:33 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aRDu3-00011K-Jn for xen-devel@lists.xen.org; Thu, 04 Feb 2016 07:00:31 +0000 Received: from [85.158.143.35] by server-3.bemta-4.messagelabs.com id 1F/D1-31122-E07F2B65; Thu, 04 Feb 2016 07:00:30 +0000 X-Env-Sender: huaitong.han@intel.com X-Msg-Ref: server-11.tower-21.messagelabs.com!1454569229!13884365!1 X-Originating-IP: [134.134.136.65] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 50976 invoked from network); 4 Feb 2016 07:00:30 -0000 Received: from mga03.intel.com (HELO mga03.intel.com) (134.134.136.65) by server-11.tower-21.messagelabs.com with SMTP; 4 Feb 2016 07:00:30 -0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP; 03 Feb 2016 23:00:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,393,1449561600"; d="scan'208";a="42184185" Received: from huaitong-desk.bj.intel.com ([10.238.135.154]) by fmsmga004.fm.intel.com with ESMTP; 03 Feb 2016 23:00:26 -0800 From: Huaitong Han To: jbeulich@suse.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, stefano.stabellini@eu.citrix.com, ian.campbell@citrix.com, wei.liu2@citrix.com, keir@xen.org Date: Thu, 4 Feb 2016 15:00:34 +0800 Message-Id: <1454569234-25283-1-git-send-email-huaitong.han@intel.com> X-Mailer: git-send-email 2.4.3 Cc: Huaitong Han , xen-devel@lists.xen.org Subject: [Xen-devel] [PATCH V10 5/5] x86/hvm: pkeys, add pkeys support for cpuid handling X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds pkeys support for cpuid handing. Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE. X86_FEATURE_OSXSAVE depends on guest X86_FEATURE_XSAVE, but cpu_has_xsave function reflects hypervisor X86_FEATURE_XSAVE, it is fixed too. Signed-off-by: Huaitong Han Reviewed-by: Jan Beulich Acked-by: Wei Liu --- Changes in v9: *Clear X86_FEATURE_OSPKE and X86_FEATURE_OSXSAVE when the condition is not satisfied. Changes in v7: *Rebase in the latest tree. *Add a comment for cpu_has_xsave adjustment. *Adjust indentation. tools/libxc/xc_cpufeature.h | 3 +++ tools/libxc/xc_cpuid_x86.c | 6 ++++-- xen/arch/x86/hvm/hvm.c | 26 +++++++++++++++++++------- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h index ee53679..866cf0b 100644 --- a/tools/libxc/xc_cpufeature.h +++ b/tools/libxc/xc_cpufeature.h @@ -144,4 +144,7 @@ #define X86_FEATURE_CLFLUSHOPT 23 /* CLFLUSHOPT instruction */ #define X86_FEATURE_CLWB 24 /* CLWB instruction */ +/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx) */ +#define X86_FEATURE_PKU 3 + #endif /* __LIBXC_CPUFEATURE_H */ diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c index c142595..5408dd0 100644 --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -430,9 +430,11 @@ static void xc_cpuid_hvm_policy(xc_interface *xch, bitmaskof(X86_FEATURE_PCOMMIT) | bitmaskof(X86_FEATURE_CLWB) | bitmaskof(X86_FEATURE_CLFLUSHOPT)); + regs[2] &= bitmaskof(X86_FEATURE_PKU); } else - regs[1] = 0; - regs[0] = regs[2] = regs[3] = 0; + regs[1] = regs[2] = 0; + + regs[0] = regs[3] = 0; break; case 0x0000000d: diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5ec2ae1..73fb54c 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4572,9 +4572,11 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, __clear_bit(X86_FEATURE_APIC & 31, edx); /* Fix up OSXSAVE. */ - if ( cpu_has_xsave ) - *ecx |= (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_OSXSAVE) ? - cpufeat_mask(X86_FEATURE_OSXSAVE) : 0; + if ( *ecx & cpufeat_mask(X86_FEATURE_XSAVE) && + (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_OSXSAVE) ) + *ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE); + else + *ecx &= ~cpufeat_mask(X86_FEATURE_OSXSAVE); /* Don't expose PCID to non-hap hvm. */ if ( !hap_enabled(d) ) @@ -4593,16 +4595,26 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, if ( !cpu_has_smap ) *ebx &= ~cpufeat_mask(X86_FEATURE_SMAP); - /* Don't expose MPX to hvm when VMX support is not available */ + /* Don't expose MPX to hvm when VMX support is not available. */ if ( !(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) || !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS) ) *ebx &= ~cpufeat_mask(X86_FEATURE_MPX); - /* Don't expose INVPCID to non-hap hvm. */ if ( !hap_enabled(d) ) - *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); + { + /* Don't expose INVPCID to non-hap hvm. */ + *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); + /* X86_FEATURE_PKU is not yet implemented for shadow paging. */ + *ecx &= ~cpufeat_mask(X86_FEATURE_PKU); + } + + if ( (*ecx & cpufeat_mask(X86_FEATURE_PKU)) && + (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PKE) ) + *ecx |= cpufeat_mask(X86_FEATURE_OSPKE); + else + *ecx &= ~cpufeat_mask(X86_FEATURE_OSPKE); - /* Don't expose PCOMMIT to hvm when VMX support is not available */ + /* Don't expose PCOMMIT to hvm when VMX support is not available. */ if ( !cpu_has_vmx_pcommit ) *ebx &= ~cpufeat_mask(X86_FEATURE_PCOMMIT); }