From patchwork Fri Feb 5 13:42:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 8234781 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3CC0BBEEED for ; Fri, 5 Feb 2016 14:04:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2260D2039E for ; Fri, 5 Feb 2016 14:04:37 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C139120390 for ; Fri, 5 Feb 2016 14:04:35 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aRgxX-00008J-3A; Fri, 05 Feb 2016 14:02:03 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aRgxV-00007l-5U for xen-devel@lists.xen.org; Fri, 05 Feb 2016 14:02:01 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id 49/CA-06010-85BA4B65; Fri, 05 Feb 2016 14:02:00 +0000 X-Env-Sender: prvs=8364524b4=Andrew.Cooper3@citrix.com X-Msg-Ref: server-10.tower-31.messagelabs.com!1454680918!20578519!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 47770 invoked from network); 5 Feb 2016 14:01:59 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-10.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 5 Feb 2016 14:01:59 -0000 X-IronPort-AV: E=Sophos;i="5.22,400,1449532800"; d="scan'208";a="329920276" From: Andrew Cooper To: Xen-devel Date: Fri, 5 Feb 2016 13:42:04 +0000 Message-ID: <1454679743-18133-12-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1454679743-18133-1-git-send-email-andrew.cooper3@citrix.com> References: <1454679743-18133-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: Andrew Cooper , Jan Beulich Subject: [Xen-devel] [PATCH v2 11/30] xen/x86: Calculate maximum host and guest featuresets X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP All of this information will be used by the toolstack to make informed levelling decisions for VMs, and by Xen to sanity check toolstack-provided information. Signed-off-by: Andrew Cooper --- CC: Jan Beulich --- xen/arch/x86/cpuid.c | 152 ++++++++++++++++++++++++++++++++++++++++++++ xen/arch/x86/setup.c | 3 + xen/include/asm-x86/cpuid.h | 17 +++++ 3 files changed, 172 insertions(+) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 30a3392..1af0e6c 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -1,13 +1,165 @@ #include #include +#include +#include +#include + +#define COMMON_1D INIT_COMMON_FEATURES const uint32_t known_features[] = INIT_KNOWN_FEATURES; const uint32_t inverted_features[] = INIT_INVERTED_FEATURES; +static const uint32_t pv_featuremask[] = INIT_PV_FEATURES; +static const uint32_t hvm_shadow_featuremask[] = INIT_HVM_SHADOW_FEATURES; +static const uint32_t hvm_hap_featuremask[] = INIT_HVM_HAP_FEATURES; + +uint32_t __read_mostly raw_featureset[FSCAPINTS]; +uint32_t __read_mostly host_featureset[FSCAPINTS]; +uint32_t __read_mostly pv_featureset[FSCAPINTS]; +uint32_t __read_mostly hvm_featureset[FSCAPINTS]; + +static void sanitise_featureset(uint32_t *fs) +{ + unsigned int i; + + for ( i = 0; i < FSCAPINTS; ++i ) + { + /* Clamp to known mask. */ + fs[i] &= known_features[i]; + } + + switch ( boot_cpu_data.x86_vendor ) + { + case X86_VENDOR_INTEL: + /* Intel clears the common bits in e1d. */ + fs[FEATURESET_e1d] &= ~COMMON_1D; + break; + + case X86_VENDOR_AMD: + /* AMD duplicates the common bits between 1d and e1d. */ + fs[FEATURESET_e1d] = ((fs[FEATURESET_1d] & COMMON_1D) | + (fs[FEATURESET_e1d] & ~COMMON_1D)); + break; + } +} + +static void calculate_raw_featureset(void) +{ + unsigned int i, max, tmp; + + max = cpuid_eax(0); + + if ( max >= 1 ) + cpuid(0x1, &tmp, &tmp, + &raw_featureset[FEATURESET_1c], + &raw_featureset[FEATURESET_1d]); + if ( max >= 7 ) + cpuid_count(0x7, 0, &tmp, + &raw_featureset[FEATURESET_7b0], + &raw_featureset[FEATURESET_7c0], + &tmp); + if ( max >= 0xd ) + cpuid_count(0xd, 1, + &raw_featureset[FEATURESET_Da1], + &tmp, &tmp, &tmp); + + max = cpuid_eax(0x80000000); + if ( max >= 0x80000001 ) + cpuid(0x80000001, &tmp, &tmp, + &raw_featureset[FEATURESET_e1c], + &raw_featureset[FEATURESET_e1d]); + if ( max >= 0x80000007 ) + cpuid(0x80000007, &tmp, &tmp, &tmp, + &raw_featureset[FEATURESET_e7d]); + if ( max >= 0x80000008 ) + cpuid(0x80000008, &tmp, + &raw_featureset[FEATURESET_e8b], + &tmp, &tmp); + + for ( i = 0; i < ARRAY_SIZE(raw_featureset); ++i ) + raw_featureset[i] ^= inverted_features[i]; +} + +static void calculate_host_featureset(void) +{ + memcpy(host_featureset, boot_cpu_data.x86_capability, + sizeof(host_featureset)); +} + +static void calculate_pv_featureset(void) +{ + unsigned int i; + + for ( i = 0; i < ARRAY_SIZE(pv_featureset); ++i ) + pv_featureset[i] = host_featureset[i] & pv_featuremask[i]; + + /* Unconditionally claim to be able to set the hypervisor bit. */ + __set_bit(X86_FEATURE_HYPERVISOR, pv_featureset); + + sanitise_featureset(pv_featureset); +} + +static void calculate_hvm_featureset(void) +{ + unsigned int i; + const uint32_t *hvm_featuremask; + + if ( !hvm_enabled ) + return; + + hvm_featuremask = hvm_funcs.hap_supported ? + hvm_hap_featuremask : hvm_shadow_featuremask; + + for ( i = 0; i < ARRAY_SIZE(hvm_featureset); ++i ) + hvm_featureset[i] = host_featureset[i] & hvm_featuremask[i]; + + /* Unconditionally claim to be able to set the hypervisor bit. */ + __set_bit(X86_FEATURE_HYPERVISOR, hvm_featureset); + + /* + * On AMD, PV guests are entirely unable to use 'sysenter' as Xen runs in + * long mode (and init_amd() has cleared it out of host capabilities), but + * HVM guests are able if running in protected mode. + */ + if ( (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && + test_bit(X86_FEATURE_SEP, raw_featureset) ) + __set_bit(X86_FEATURE_SEP, hvm_featureset); + + /* + * With VT-x, some features are only supported by Xen if dedicated + * hardware support is also available. + */ + if ( cpu_has_vmx ) + { + if ( !(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) || + !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS) ) + __clear_bit(X86_FEATURE_MPX, hvm_featureset); + + if ( !cpu_has_vmx_xsaves ) + __clear_bit(X86_FEATURE_XSAVES, hvm_featureset); + + if ( !cpu_has_vmx_pcommit ) + __clear_bit(X86_FEATURE_PCOMMIT, hvm_featureset); + } + + sanitise_featureset(pv_featureset); +} + +void calculate_featuresets(void) +{ + calculate_raw_featureset(); + calculate_host_featureset(); + calculate_pv_featureset(); + calculate_hvm_featureset(); +} + static void __maybe_unused build_assertions(void) { BUILD_BUG_ON(ARRAY_SIZE(known_features) != FSCAPINTS); BUILD_BUG_ON(ARRAY_SIZE(inverted_features) != FSCAPINTS); + BUILD_BUG_ON(ARRAY_SIZE(pv_featuremask) != FSCAPINTS); + BUILD_BUG_ON(ARRAY_SIZE(hvm_shadow_featuremask) != FSCAPINTS); + BUILD_BUG_ON(ARRAY_SIZE(hvm_hap_featuremask) != FSCAPINTS); } /* diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 76c7b0f..50e4e51 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -50,6 +50,7 @@ #include #include #include +#include /* opt_nosmp: If true, secondary processors are ignored. */ static bool_t __initdata opt_nosmp; @@ -1437,6 +1438,8 @@ void __init noreturn __start_xen(unsigned long mbi_p) "Multiple initrd candidates, picking module #%u\n", initrdidx); + calculate_featuresets(); + /* * Temporarily clear SMAP in CR4 to allow user-accesses in construct_dom0(). * This saves a large number of corner cases interactions with diff --git a/xen/include/asm-x86/cpuid.h b/xen/include/asm-x86/cpuid.h index 341dbc1..18ba95b 100644 --- a/xen/include/asm-x86/cpuid.h +++ b/xen/include/asm-x86/cpuid.h @@ -5,12 +5,29 @@ #define FSCAPINTS FEATURESET_NR_ENTRIES +#define FEATURESET_1d 0 /* 0x00000001.edx */ +#define FEATURESET_1c 1 /* 0x00000001.ecx */ +#define FEATURESET_e1d 2 /* 0x80000001.edx */ +#define FEATURESET_e1c 3 /* 0x80000001.ecx */ +#define FEATURESET_Da1 4 /* 0x0000000d:1.eax */ +#define FEATURESET_7b0 5 /* 0x00000007:0.ebx */ +#define FEATURESET_7c0 6 /* 0x00000007:0.ecx */ +#define FEATURESET_e7d 7 /* 0x80000007.edx */ +#define FEATURESET_e8b 8 /* 0x80000008.ebx */ + #ifndef __ASSEMBLY__ #include extern const uint32_t known_features[FSCAPINTS]; extern const uint32_t inverted_features[FSCAPINTS]; +extern uint32_t raw_featureset[FSCAPINTS]; +extern uint32_t host_featureset[FSCAPINTS]; +extern uint32_t pv_featureset[FSCAPINTS]; +extern uint32_t hvm_featureset[FSCAPINTS]; + +void calculate_featuresets(void); + #endif /* __ASSEMBLY__ */ #endif /* !__X86_CPUID_H__ */